1 !sum
2 # Float <-> Int conversions
3 # float32 -> int32
4 - go: ConvertToInt32
5 regexpTag: "convert"
6 asm: "VCVTTP[SD]2DQ"
7 in:
8 - &fp
9 go: $t
10 base: float
11 out:
12 - &i32
13 go: $u
14 base: int
15 elemBits: 32
16 # float32 -> uint32
17 - go: ConvertToUint32
18 regexpTag: "convert"
19 asm: "VCVTTP[SD]2UDQ"
20 in:
21 - *fp
22 out:
23 - &u32
24 go: $u
25 base: uint
26 elemBits: 32
27 # float32|float64 -> int64
28 - go: ConvertToInt64
29 regexpTag: "convert"
30 asm: "VCVTTPD2QQ"
31 in:
32 - *fp
33 out:
34 - &i64
35 go: $u
36 base: int
37 elemBits: 64
38 - go: ConvertToInt64
39 regexpTag: "convert"
40 asm: "VCVTTPS2QQ"
41 in:
42 - *fp
43 out:
44 - go: $u
45 base: int
46 elemBits: 64
47 bits: 256|512
48 # float32|float64 -> uint64
49 - go: ConvertToUint64
50 regexpTag: "convert"
51 asm: "VCVTTPD2UQQ"
52 in:
53 - *fp
54 out:
55 - &u64
56 go: $u
57 base: uint
58 elemBits: 64
59 - go: ConvertToUint64
60 regexpTag: "convert"
61 asm: "VCVTTPS2UQQ"
62 in:
63 - *fp
64 out:
65 - go: $u
66 base: uint
67 elemBits: 64
68 bits: 256|512
69 # int -> float32
70 - go: ConvertToFloat32
71 regexpTag: "convert"
72 asm: "VCVT[DQ]Q2PS"
73 in: &int
74 - go: $i
75 base: int
76 out:
77 - *fp
78 # int -> float64
79 - go: ConvertToFloat64
80 regexpTag: "convert"
81 asm: "VCVTQQ2PD"
82 in: *int
83 out:
84 - *fp
85 - go: ConvertToFloat64
86 regexpTag: "convert"
87 asm: "VCVTDQ2PD"
88 in: *int
89 out:
90 - base: float
91 bits: 256|512
92 # uint -> float32
93 - go: ConvertToFloat32
94 regexpTag: "convert"
95 asm: "VCVTU[DQ]Q2PS"
96 in: &uint
97 - go: $u
98 base: uint
99 out:
100 - *fp
101 # uint -> float64
102 - go: ConvertToFloat64
103 regexpTag: "convert"
104 asm: "VCVTUQQ2PD"
105 in: *uint
106 out:
107 - *fp
108 - go: ConvertToFloat64
109 regexpTag: "convert"
110 asm: "VCVTUDQ2PD"
111 in: *uint
112 out:
113 - base: float
114 bits: 256|512
115 # float64 -> float32
116 - go: ConvertToFloat32
117 regexpTag: "convert"
118 asm: "VCVTPD2PS"
119 addDoc:
120 !string |-
121 // The result vector's elements are rounded to the nearest value.
122 in: &fp64
123 - base: float
124 elemBits: 64
125 out: &fp32
126 - base: float
127 elemBits: 32
128 # float32 -> float64
129 - go: ConvertToFloat64
130 regexpTag: "convert"
131 asm: "VCVTPS2PD"
132 in: *fp32
133 out:
134 - base: float
135 elemBits: 64
136 bits: 256|512
137
138 # Widening integer conversions.
139 # uint8 -> uint16
140 - go: ExtendToUint16
141 addDoc: &zeroExtendDoc
142 !string |-
143 // The result vector's elements are zero-extended.
144 regexpTag: "convert"
145 asm: "VPMOVZXBW"
146 in:
147 - &u8x16
148 base: uint
149 elemBits: 8
150 bits: 128
151 out:
152 - &u16x16
153 base: uint
154 elemBits: 16
155 bits: 256
156 - go: ExtendToUint16
157 regexpTag: "convert"
158 asm: "VPMOVZXBW"
159 addDoc: *zeroExtendDoc
160 in:
161 - &u8x32
162 base: uint
163 elemBits: 8
164 bits: 256
165 out:
166 - &u16x32
167 base: uint
168 elemBits: 16
169 bits: 512
170 # int8 -> int16
171 - go: ExtendToInt16
172 regexpTag: "convert"
173 asm: "VPMOVSXBW"
174 addDoc: &signExtendDoc
175 !string |-
176 // The result vector's elements are sign-extended.
177 in:
178 - &i8x16
179 base: int
180 elemBits: 8
181 bits: 128
182 out:
183 - &i16x16
184 base: int
185 elemBits: 16
186 bits: 256
187 - go: ExtendToInt16
188 regexpTag: "convert"
189 asm: "VPMOVSXBW"
190 addDoc: *signExtendDoc
191 in:
192 - &i8x32
193 base: int
194 elemBits: 8
195 bits: 256
196 out:
197 - &i16x32
198 base: int
199 elemBits: 16
200 bits: 512
201 # uint16->uint32
202 - go: ExtendToUint32
203 regexpTag: "convert"
204 asm: "VPMOVZXWD"
205 addDoc: *zeroExtendDoc
206 in:
207 - &u16x8
208 base: uint
209 elemBits: 16
210 bits: 128
211 out:
212 - &u32x8
213 base: uint
214 elemBits: 32
215 bits: 256
216 - go: ExtendToUint32
217 regexpTag: "convert"
218 asm: "VPMOVZXWD"
219 addDoc: *zeroExtendDoc
220 in:
221 - *u16x16
222 out:
223 - &u32x16
224 base: uint
225 elemBits: 32
226 bits: 512
227 # int16->int32
228 - go: ExtendToInt32
229 regexpTag: "convert"
230 asm: "VPMOVSXWD"
231 addDoc: *signExtendDoc
232 in:
233 - &i16x8
234 base: int
235 elemBits: 16
236 bits: 128
237 out:
238 - &i32x8
239 base: int
240 elemBits: 32
241 bits: 256
242 - go: ExtendToInt32
243 regexpTag: "convert"
244 asm: "VPMOVSXWD"
245 addDoc: *signExtendDoc
246 in:
247 - *i16x16
248 out:
249 - &i32x16
250 base: int
251 elemBits: 32
252 bits: 512
253 # uint32 -> uint64
254 - go: ExtendToUint64
255 regexpTag: "convert"
256 asm: "VPMOVZXDQ"
257 addDoc: *zeroExtendDoc
258 in:
259 - &u32x4
260 base: uint
261 elemBits: 32
262 bits: 128
263 out:
264 - &u64x4
265 base: uint
266 elemBits: 64
267 bits: 256
268 - go: ExtendToUint64
269 regexpTag: "convert"
270 asm: "VPMOVZXDQ"
271 addDoc: *zeroExtendDoc
272 in:
273 - *u32x8
274 out:
275 - &u64x8
276 base: uint
277 elemBits: 64
278 bits: 512
279 # int32 -> int64
280 - go: ExtendToInt64
281 regexpTag: "convert"
282 asm: "VPMOVSXDQ"
283 addDoc: *signExtendDoc
284 in:
285 - &i32x4
286 base: int
287 elemBits: 32
288 bits: 128
289 out:
290 - &i64x4
291 base: int
292 elemBits: 64
293 bits: 256
294 - go: ExtendToInt64
295 regexpTag: "convert"
296 asm: "VPMOVSXDQ"
297 addDoc: *signExtendDoc
298 in:
299 - *i32x8
300 out:
301 - &i64x8
302 base: int
303 elemBits: 64
304 bits: 512
305 # uint16 -> uint64
306 - go: ExtendToUint64
307 regexpTag: "convert"
308 asm: "VPMOVZXWQ"
309 addDoc: *zeroExtendDoc
310 in:
311 - *u16x8
312 out:
313 - *u64x8
314 # int16 -> int64
315 - go: ExtendToInt64
316 regexpTag: "convert"
317 asm: "VPMOVSXWQ"
318 addDoc: *signExtendDoc
319 in:
320 - *i16x8
321 out:
322 - *i64x8
323 # uint8 -> uint32
324 - go: ExtendToUint32
325 regexpTag: "convert"
326 asm: "VPMOVZXBD"
327 addDoc: *zeroExtendDoc
328 in:
329 - *u8x16
330 out:
331 - *u32x16
332 # int8 -> int32
333 - go: ExtendToInt32
334 regexpTag: "convert"
335 asm: "VPMOVSXBD"
336 addDoc: *signExtendDoc
337 in:
338 - *i8x16
339 out:
340 - *i32x16
341 # Truncating conversions
342 - go: TruncateToInt8
343 regexpTag: "convert"
344 asm: "VPMOV[WDQ]B"
345 addDoc: &truncDocZeroUpper
346 !string |-
347 // Conversion is done with truncation on the vector elements.
348 // Results are packed to low elements in the returned vector, its upper elements are zero-cleared.
349 in:
350 - base: int
351 out:
352 - base: int
353 bits: 128
354 - go: TruncateToUint8
355 regexpTag: "convert"
356 asm: "VPMOV[WDQ]B"
357 addDoc: *truncDocZeroUpper
358 in:
359 - base: uint
360 out:
361 - base: uint
362 bits: 128
363 - go: TruncateToInt8
364 regexpTag: "convert"
365 asm: "VPMOV[WDQ]B"
366 addDoc: &truncDoc
367 !string |-
368 // Conversion is done with truncation on the vector elements.
369 in:
370 - base: int
371 out:
372 - base: int
373 bits: 256|512
374 - go: TruncateToUint8
375 regexpTag: "convert"
376 asm: "VPMOV[WDQ]B"
377 addDoc: *truncDoc
378 in:
379 - base: uint
380 out:
381 - base: uint
382 bits: 256|512
383 - go: TruncateToInt16
384 regexpTag: "convert"
385 asm: "VPMOV[DQ]W"
386 addDoc: *truncDoc
387 in:
388 - base: int
389 out:
390 - base: int
391 - go: TruncateToUint16
392 regexpTag: "convert"
393 asm: "VPMOV[DQ]W"
394 addDoc: *truncDoc
395 in:
396 - base: uint
397 out:
398 - base: uint
399 - go: TruncateToInt32
400 regexpTag: "convert"
401 asm: "VPMOVQD"
402 addDoc: *truncDoc
403 in:
404 - base: int
405 out:
406 - base: int
407 - go: TruncateToUint32
408 regexpTag: "convert"
409 asm: "VPMOVQD"
410 addDoc: *truncDoc
411 in:
412 - base: uint
413 out:
414 - base: uint
415 # Saturated conversions.
416 - go: SaturateToInt8
417 regexpTag: "convert"
418 asm: "VPMOVS[WDQ]B"
419 addDoc: &satDocZeroUpper
420 !string |-
421 // Conversion is done with saturation on the vector elements.
422 // Results are packed to low elements in the returned vector, its upper elements are zero-cleared.
423 in:
424 - base: int
425 out:
426 - base: int
427 bits: 128
428 - go: SaturateToUint8
429 regexpTag: "convert"
430 asm: "VPMOVS[WDQ]B"
431 addDoc: *satDocZeroUpper
432 in:
433 - base: int
434 out:
435 - base: int
436 bits: 128
437 - go: SaturateToInt8
438 regexpTag: "convert"
439 asm: "VPMOVS[WDQ]B"
440 addDoc: &satDoc
441 !string |-
442 // Conversion is done with saturation on the vector elements.
443 in:
444 - base: int
445 out:
446 - base: int
447 bits: 256|512
448 - go: SaturateToUint8
449 regexpTag: "convert"
450 asm: "VPMOVUS[WDQ]B"
451 addDoc: *satDoc
452 in:
453 - base: uint
454 out:
455 - base: uint
456 bits: 256|512
457 - go: SaturateToInt16
458 regexpTag: "convert"
459 asm: "VPMOVS[DQ]W"
460 addDoc: *satDoc
461 in:
462 - base: int
463 out:
464 - base: int
465 - go: SaturateToUint16
466 regexpTag: "convert"
467 asm: "VPMOVUS[DQ]W"
468 addDoc: *satDoc
469 in:
470 - base: uint
471 out:
472 - base: uint
473 - go: SaturateToInt32
474 regexpTag: "convert"
475 asm: "VPMOVSQD"
476 addDoc: *satDoc
477 in:
478 - base: int
479 out:
480 - base: int
481 - go: SaturateToUint32
482 regexpTag: "convert"
483 asm: "VPMOVUSQD"
484 addDoc: *satDoc
485 in:
486 - base: uint
487 out:
488 - base: uint
489 # Truncating saturated packed
490 - go: SaturateToInt16Concat
491 regexpTag: "convert"
492 asm: "VPACKSSDW"
493 addDoc: &satDocConcat
494 !string |-
495 // With each 128-bit as a group:
496 // The converted group from the first input vector will be packed to the lower part of the result vector,
497 // the converted group from the second input vector will be packed to the upper part of the result vector.
498 // Conversion is done with saturation on the vector elements.
499 in:
500 - base: int
501 - base: int
502 out:
503 - base: int
504 - go: SaturateToUint16Concat
505 regexpTag: "convert"
506 asm: "VPACKUSDW"
507 addDoc: *satDocConcat
508 in:
509 - base: uint
510 - base: uint
511 out:
512 - base: uint
513
514 # low-part only conversions.
515 # uint8->uint16
516 - go: ExtendLo8ToUint16x8
517 regexpTag: "convert"
518 asm: "VPMOVZXBW"
519 addDoc: *zeroExtendDoc
520 in:
521 - *u8x16
522 out:
523 - *u16x8
524 # int8->int16
525 - go: ExtendLo8ToInt16x8
526 regexpTag: "convert"
527 asm: "VPMOVSXBW"
528 addDoc: *signExtendDoc
529 in:
530 - *i8x16
531 out:
532 - *i16x8
533 # uint16->uint32
534 - go: ExtendLo4ToUint32x4
535 regexpTag: "convert"
536 asm: "VPMOVZXWD"
537 addDoc: *zeroExtendDoc
538 in:
539 - *u16x8
540 out:
541 - *u32x4
542 # int16->int32
543 - go: ExtendLo4ToInt32x4
544 regexpTag: "convert"
545 asm: "VPMOVSXWD"
546 addDoc: *signExtendDoc
547 in:
548 - *i16x8
549 out:
550 - *i32x4
551 # uint32 -> uint64
552 - go: ExtendLo2ToUint64x2
553 regexpTag: "convert"
554 asm: "VPMOVZXDQ"
555 addDoc: *zeroExtendDoc
556 in:
557 - *u32x4
558 out:
559 - &u64x2
560 base: uint
561 elemBits: 64
562 bits: 128
563 # int32 -> int64
564 - go: ExtendLo2ToInt64x2
565 regexpTag: "convert"
566 asm: "VPMOVSXDQ"
567 addDoc: *signExtendDoc
568 in:
569 - *i32x4
570 out:
571 - &i64x2
572 base: int
573 elemBits: 64
574 bits: 128
575 # uint16 -> uint64
576 - go: ExtendLo2ToUint64x2
577 regexpTag: "convert"
578 asm: "VPMOVZXWQ"
579 addDoc: *zeroExtendDoc
580 in:
581 - *u16x8
582 out:
583 - *u64x2
584 - go: ExtendLo4ToUint64x4
585 regexpTag: "convert"
586 asm: "VPMOVZXWQ"
587 addDoc: *zeroExtendDoc
588 in:
589 - *u16x8
590 out:
591 - *u64x4
592 # int16 -> int64
593 - go: ExtendLo2ToInt64x2
594 regexpTag: "convert"
595 asm: "VPMOVSXWQ"
596 addDoc: *signExtendDoc
597 in:
598 - *i16x8
599 out:
600 - *i64x2
601 - go: ExtendLo4ToInt64x4
602 regexpTag: "convert"
603 asm: "VPMOVSXWQ"
604 addDoc: *signExtendDoc
605 in:
606 - *i16x8
607 out:
608 - *i64x4
609 # uint8 -> uint32
610 - go: ExtendLo4ToUint32x4
611 regexpTag: "convert"
612 asm: "VPMOVZXBD"
613 addDoc: *zeroExtendDoc
614 in:
615 - *u8x16
616 out:
617 - *u32x4
618 - go: ExtendLo8ToUint32x8
619 regexpTag: "convert"
620 asm: "VPMOVZXBD"
621 addDoc: *zeroExtendDoc
622 in:
623 - *u8x16
624 out:
625 - *u32x8
626 # int8 -> int32
627 - go: ExtendLo4ToInt32x4
628 regexpTag: "convert"
629 asm: "VPMOVSXBD"
630 addDoc: *signExtendDoc
631 in:
632 - *i8x16
633 out:
634 - *i32x4
635 - go: ExtendLo8ToInt32x8
636 regexpTag: "convert"
637 asm: "VPMOVSXBD"
638 addDoc: *signExtendDoc
639 in:
640 - *i8x16
641 out:
642 - *i32x8
643 # uint8 -> uint64
644 - go: ExtendLo2ToUint64x2
645 regexpTag: "convert"
646 asm: "VPMOVZXBQ"
647 addDoc: *zeroExtendDoc
648 in:
649 - *u8x16
650 out:
651 - *u64x2
652 - go: ExtendLo4ToUint64x4
653 regexpTag: "convert"
654 asm: "VPMOVZXBQ"
655 addDoc: *zeroExtendDoc
656 in:
657 - *u8x16
658 out:
659 - *u64x4
660 - go: ExtendLo8ToUint64x8
661 regexpTag: "convert"
662 asm: "VPMOVZXBQ"
663 addDoc: *zeroExtendDoc
664 in:
665 - *u8x16
666 out:
667 - *u64x8
668 # int8 -> int64
669 - go: ExtendLo2ToInt64x2
670 regexpTag: "convert"
671 asm: "VPMOVSXBQ"
672 addDoc: *signExtendDoc
673 in:
674 - *i8x16
675 out:
676 - *i64x2
677 - go: ExtendLo4ToInt64x4
678 regexpTag: "convert"
679 asm: "VPMOVSXBQ"
680 addDoc: *signExtendDoc
681 in:
682 - *i8x16
683 out:
684 - *i64x4
685 - go: ExtendLo8ToInt64x8
686 regexpTag: "convert"
687 asm: "VPMOVSXBQ"
688 addDoc: *signExtendDoc
689 in:
690 - *i8x16
691 out:
692 - *i64x8
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