a.out.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  )
    10  
    11  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p loong64
    12  
    13  const (
    14  	NSNAME = 8
    15  	NSYM   = 50
    16  	NREG   = 32 // number of general registers
    17  	NFREG  = 32 // number of floating point registers
    18  	NVREG  = 32 // number of LSX registers
    19  	NXREG  = 32 // number of LASX registers
    20  )
    21  
    22  const (
    23  	REG_R0 = obj.RBaseLOONG64 + iota // must be a multiple of 32
    24  	REG_R1
    25  	REG_R2
    26  	REG_R3
    27  	REG_R4
    28  	REG_R5
    29  	REG_R6
    30  	REG_R7
    31  	REG_R8
    32  	REG_R9
    33  	REG_R10
    34  	REG_R11
    35  	REG_R12
    36  	REG_R13
    37  	REG_R14
    38  	REG_R15
    39  	REG_R16
    40  	REG_R17
    41  	REG_R18
    42  	REG_R19
    43  	REG_R20
    44  	REG_R21
    45  	REG_R22
    46  	REG_R23
    47  	REG_R24
    48  	REG_R25
    49  	REG_R26
    50  	REG_R27
    51  	REG_R28
    52  	REG_R29
    53  	REG_R30
    54  	REG_R31
    55  
    56  	REG_F0 // must be a multiple of 32
    57  	REG_F1
    58  	REG_F2
    59  	REG_F3
    60  	REG_F4
    61  	REG_F5
    62  	REG_F6
    63  	REG_F7
    64  	REG_F8
    65  	REG_F9
    66  	REG_F10
    67  	REG_F11
    68  	REG_F12
    69  	REG_F13
    70  	REG_F14
    71  	REG_F15
    72  	REG_F16
    73  	REG_F17
    74  	REG_F18
    75  	REG_F19
    76  	REG_F20
    77  	REG_F21
    78  	REG_F22
    79  	REG_F23
    80  	REG_F24
    81  	REG_F25
    82  	REG_F26
    83  	REG_F27
    84  	REG_F28
    85  	REG_F29
    86  	REG_F30
    87  	REG_F31
    88  
    89  	REG_FCSR0 // must be a multiple of 32
    90  	REG_FCSR1
    91  	REG_FCSR2
    92  	REG_FCSR3 // only four registers are needed
    93  	REG_FCSR4
    94  	REG_FCSR5
    95  	REG_FCSR6
    96  	REG_FCSR7
    97  	REG_FCSR8
    98  	REG_FCSR9
    99  	REG_FCSR10
   100  	REG_FCSR11
   101  	REG_FCSR12
   102  	REG_FCSR13
   103  	REG_FCSR14
   104  	REG_FCSR15
   105  	REG_FCSR16
   106  	REG_FCSR17
   107  	REG_FCSR18
   108  	REG_FCSR19
   109  	REG_FCSR20
   110  	REG_FCSR21
   111  	REG_FCSR22
   112  	REG_FCSR23
   113  	REG_FCSR24
   114  	REG_FCSR25
   115  	REG_FCSR26
   116  	REG_FCSR27
   117  	REG_FCSR28
   118  	REG_FCSR29
   119  	REG_FCSR30
   120  	REG_FCSR31
   121  
   122  	REG_FCC0 // must be a multiple of 32
   123  	REG_FCC1
   124  	REG_FCC2
   125  	REG_FCC3
   126  	REG_FCC4
   127  	REG_FCC5
   128  	REG_FCC6
   129  	REG_FCC7 // only eight registers are needed
   130  	REG_FCC8
   131  	REG_FCC9
   132  	REG_FCC10
   133  	REG_FCC11
   134  	REG_FCC12
   135  	REG_FCC13
   136  	REG_FCC14
   137  	REG_FCC15
   138  	REG_FCC16
   139  	REG_FCC17
   140  	REG_FCC18
   141  	REG_FCC19
   142  	REG_FCC20
   143  	REG_FCC21
   144  	REG_FCC22
   145  	REG_FCC23
   146  	REG_FCC24
   147  	REG_FCC25
   148  	REG_FCC26
   149  	REG_FCC27
   150  	REG_FCC28
   151  	REG_FCC29
   152  	REG_FCC30
   153  	REG_FCC31
   154  
   155  	// LSX: 128-bit vector register
   156  	REG_V0
   157  	REG_V1
   158  	REG_V2
   159  	REG_V3
   160  	REG_V4
   161  	REG_V5
   162  	REG_V6
   163  	REG_V7
   164  	REG_V8
   165  	REG_V9
   166  	REG_V10
   167  	REG_V11
   168  	REG_V12
   169  	REG_V13
   170  	REG_V14
   171  	REG_V15
   172  	REG_V16
   173  	REG_V17
   174  	REG_V18
   175  	REG_V19
   176  	REG_V20
   177  	REG_V21
   178  	REG_V22
   179  	REG_V23
   180  	REG_V24
   181  	REG_V25
   182  	REG_V26
   183  	REG_V27
   184  	REG_V28
   185  	REG_V29
   186  	REG_V30
   187  	REG_V31
   188  
   189  	// LASX: 256-bit vector register
   190  	REG_X0
   191  	REG_X1
   192  	REG_X2
   193  	REG_X3
   194  	REG_X4
   195  	REG_X5
   196  	REG_X6
   197  	REG_X7
   198  	REG_X8
   199  	REG_X9
   200  	REG_X10
   201  	REG_X11
   202  	REG_X12
   203  	REG_X13
   204  	REG_X14
   205  	REG_X15
   206  	REG_X16
   207  	REG_X17
   208  	REG_X18
   209  	REG_X19
   210  	REG_X20
   211  	REG_X21
   212  	REG_X22
   213  	REG_X23
   214  	REG_X24
   215  	REG_X25
   216  	REG_X26
   217  	REG_X27
   218  	REG_X28
   219  	REG_X29
   220  	REG_X30
   221  	REG_X31
   222  
   223  	REG_SPECIAL = REG_FCSR0
   224  
   225  	REGZERO = REG_R0 // set to zero
   226  	REGLINK = REG_R1
   227  	REGSP   = REG_R3
   228  	REGRET  = REG_R20 // not use
   229  	REGARG  = -1      // -1 disables passing the first argument in register
   230  	REGRT1  = REG_R20 // reserved for runtime, duffzero and duffcopy
   231  	REGRT2  = REG_R21 // reserved for runtime, duffcopy
   232  	REGCTXT = REG_R29 // context for closures
   233  	REGG    = REG_R22 // G in loong64
   234  	REGTMP  = REG_R30 // used by the assembler
   235  	FREGRET = REG_F0  // not use
   236  )
   237  
   238  var LOONG64DWARFRegisters = map[int16]int16{}
   239  
   240  func init() {
   241  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   242  	f := func(from, to, base int16) {
   243  		for r := int16(from); r <= to; r++ {
   244  			LOONG64DWARFRegisters[r] = (r - from) + base
   245  		}
   246  	}
   247  	f(REG_R0, REG_R31, 0)
   248  	f(REG_F0, REG_F31, 32)
   249  
   250  	// The lower bits of V and X registers are alias to F registers
   251  	f(REG_V0, REG_V31, 32)
   252  	f(REG_X0, REG_X31, 32)
   253  }
   254  
   255  const (
   256  	BIG = 2046
   257  )
   258  
   259  const (
   260  	// mark flags
   261  	LABEL  = 1 << 0
   262  	LEAF   = 1 << 1
   263  	SYNC   = 1 << 2
   264  	BRANCH = 1 << 3
   265  )
   266  
   267  // Arrangement for Loong64 SIMD instructions
   268  const (
   269  	// arrangement types
   270  	ARNG_32B int16 = iota
   271  	ARNG_16H
   272  	ARNG_8W
   273  	ARNG_4V
   274  	ARNG_2Q
   275  	ARNG_16B
   276  	ARNG_8H
   277  	ARNG_4W
   278  	ARNG_2V
   279  	ARNG_B
   280  	ARNG_H
   281  	ARNG_W
   282  	ARNG_V
   283  	ARNG_BU
   284  	ARNG_HU
   285  	ARNG_WU
   286  	ARNG_VU
   287  )
   288  
   289  // LoongArch64 SIMD extension type
   290  const (
   291  	LSX int16 = iota
   292  	LASX
   293  )
   294  
   295  // bits 0-4 indicates register: Vn or Xn
   296  // bits 5-9 indicates arrangement: <T>
   297  // bits 10 indicates SMID type: 0: LSX, 1: LASX
   298  const (
   299  	REG_ARNG = obj.RBaseLOONG64 + (1 << 10) + (iota << 11) // Vn.<T>
   300  	REG_ELEM                                               // Vn.<T>[index]
   301  	REG_ELEM_END
   302  )
   303  
   304  const (
   305  	EXT_REG_SHIFT = 0
   306  	EXT_REG_MASK  = 0x1f
   307  
   308  	EXT_TYPE_SHIFT = 5
   309  	EXT_TYPE_MASK  = 0x1f
   310  
   311  	EXT_SIMDTYPE_SHIFT = 10
   312  	EXT_SIMDTYPE_MASK  = 0x1
   313  )
   314  
   315  const (
   316  	REG_LAST = REG_ELEM_END // the last defined register
   317  )
   318  
   319  //go:generate go run ../mkcnames.go -i a.out.go -o cnames.go -p loong64
   320  const (
   321  	C_NONE = iota
   322  	C_REG
   323  	C_FREG
   324  	C_FCSRREG
   325  	C_FCCREG
   326  	C_VREG
   327  	C_XREG
   328  	C_ARNG // Vn.<T>
   329  	C_ELEM // Vn.<T>[index]
   330  
   331  	C_ZCON
   332  	C_U1CON      // 1 bit unsigned constant
   333  	C_U2CON      // 2 bit unsigned constant
   334  	C_U3CON      // 3 bit unsigned constant
   335  	C_U4CON      // 4 bit unsigned constant
   336  	C_U5CON      // 5 bit unsigned constant
   337  	C_U6CON      // 6 bit unsigned constant
   338  	C_U7CON      // 7 bit unsigned constant
   339  	C_U8CON      // 8 bit unsigned constant
   340  	C_S5CON      // 5 bit signed constant
   341  	C_US12CON    // same as C_S12CON, increase the priority of C_S12CON in special cases.
   342  	C_UU12CON    // same as C_U12CON, increase the priority of C_U12CON in special cases.
   343  	C_S12CON     // 12 bit signed constant, -0x800 < v <= 0x7ff
   344  	C_U12CON     // 12 bit unsigned constant, 0 < v <= 0xfff
   345  	C_12CON      // 12 bit signed constant, or 12 bit unsigned constant
   346  	C_S13CON20_0 // 13 bit signed constant, low 12 bits 0
   347  	C_S13CON     // 13 bit signed constant
   348  	C_U13CON20_0 // 13 bit unsigned constant, low 12 bits 0
   349  	C_U13CON     // 13 bit unsigned constant
   350  	C_13CON      // 13 bit signed constant, or 13 bit unsigned constant
   351  	C_U15CON     // 15 bit unsigned constant
   352  	C_U15CON20_0 // 15 bit unsigned constant, low 12 bits 0
   353  	C_32CON20_0  // 32 bit signed, low 12 bits 0
   354  	C_32CON      // other 32 bit signed
   355  
   356  	// 64 bit signed, lo32 bits 0, hi20 bits are not 0, hi12 bits can
   357  	// be obtained by sign extension of the hi20 bits.
   358  	C_DCON20S_0
   359  	// 64 bit signed, lo52 bits 0, hi12 bits are not 0.
   360  	C_DCON12_0
   361  	// 64 bit signed, lo32 bits 0, hi32 bits are not 0.
   362  	C_DCON32_0
   363  	// 64 bit signed, lo12 bits 0, lo20 bits are not 0, hi20 bits can be
   364  	// obtained by sign extension of the lo20 bits, other bits are not 0.
   365  	C_DCON12_20S
   366  	// 64 bit signed, lo12 bits 0, hi20 bits are not 0, hi12 bits can be
   367  	// obtained by sign extension of the hi20 bits, other bits are not 0.
   368  	C_DCON20S_20
   369  	// 64 bit signed, lo12 bits 0, other bits are not 0.
   370  	C_DCON32_20
   371  	// 64 bit signed, lo12 bits are not 0, 12~51 bits can be obtained
   372  	// by sign extension of the lo12 bits, other bits are not 0.
   373  	C_DCON12_12S
   374  	// 64 bit signed, hi20 bits and lo12 bits are not 0, hi12 bits can
   375  	// be obtained by sign extension of the hi20 bits, lo20 bits can
   376  	// be obtained by sign extension of the lo12 bits.
   377  	C_DCON20S_12S
   378  	// 64 bit signed, lo12 bits are not 0, lo20 bits can be obtained by sign
   379  	// extension of the lo12 bits, other bits are not 0.
   380  	C_DCON32_12S
   381  	// 64 bit signed, lo20 and lo12 bits are not 0, hi20 bits can be obtained by sign
   382  	// extension of the lo20 bits. other bits are not 0.
   383  	C_DCON12_32S
   384  	// 64 bit signed, hi20 bits are not 0, hi12 bits can be obtained by sign
   385  	// extension of the hi20 bits, lo32 bits are not 0.
   386  	C_DCON20S_32
   387  	// 64 bit signed, 12~51 bits 0, other bits are not 0.
   388  	C_DCON12_12U
   389  	// 64 bit signed, lo20 bits 0, hi20 bits are not 0, hi12 bits can be
   390  	// obtained by sign extension of the hi20 bits, lo12 bits are not 0.
   391  	C_DCON20S_12U
   392  	// 64 bit signed, lo20 bits 0, other bits are not 0.
   393  	C_DCON32_12U
   394  	// other 64
   395  	C_DCON
   396  
   397  	C_SACON   // $n(REG) where n <= int12
   398  	C_LACON   // $n(REG) where int12 < n <= int32
   399  	C_DACON   // $n(REG) where int32 < n
   400  	C_EXTADDR // external symbol address
   401  	C_BRAN
   402  	C_SAUTO
   403  	C_LAUTO
   404  	C_ZOREG
   405  	C_SOREG
   406  	C_LOREG
   407  	C_ROFF // register offset
   408  	C_ADDR
   409  	C_TLS_LE
   410  	C_TLS_IE
   411  	C_GOTADDR
   412  	C_TEXTSIZE
   413  
   414  	C_GOK
   415  	C_NCLASS // must be the last
   416  )
   417  
   418  const (
   419  	AABSD = obj.ABaseLoong64 + obj.A_ARCHSPECIFIC + iota
   420  	AABSF
   421  	AADD
   422  	AADDD
   423  	AADDF
   424  	AADDU
   425  
   426  	AADDW
   427  	AAND
   428  	ABEQ
   429  	ABGEZ
   430  	ABLEZ
   431  	ABGTZ
   432  	ABLTZ
   433  	ABFPF
   434  	ABFPT
   435  
   436  	ABNE
   437  	ABREAK
   438  
   439  	ACMPEQD
   440  	ACMPEQF
   441  
   442  	ACMPGED // ACMPGED -> fcmp.sle.d
   443  	ACMPGEF // ACMPGEF -> fcmp.sle.s
   444  	ACMPGTD // ACMPGTD -> fcmp.slt.d
   445  	ACMPGTF // ACMPGTF -> fcmp.slt.s
   446  
   447  	ALU12IW
   448  	ALU32ID
   449  	ALU52ID
   450  	APCALAU12I
   451  	APCADDU12I
   452  	AJIRL
   453  	ABGE
   454  	ABLT
   455  	ABLTU
   456  	ABGEU
   457  
   458  	ADIV
   459  	ADIVD
   460  	ADIVF
   461  	ADIVU
   462  	ADIVW
   463  
   464  	ALL
   465  	ALLV
   466  
   467  	ALUI
   468  
   469  	AMOVB
   470  	AMOVBU
   471  
   472  	AMOVD
   473  	AMOVDF
   474  	AMOVDW
   475  	AMOVF
   476  	AMOVFD
   477  	AMOVFW
   478  
   479  	AMOVH
   480  	AMOVHU
   481  	AMOVW
   482  
   483  	AMOVWD
   484  	AMOVWF
   485  
   486  	AMUL
   487  	AMULD
   488  	AMULF
   489  	AMULU
   490  	AMULH
   491  	AMULHU
   492  	AMULW
   493  	ANEGD
   494  	ANEGF
   495  
   496  	ANEGW
   497  	ANEGV
   498  
   499  	ANOOP // hardware nop
   500  	ANOR
   501  	AOR
   502  	AREM
   503  	AREMU
   504  
   505  	ARFE
   506  
   507  	ASC
   508  	ASCV
   509  
   510  	ASGT
   511  	ASGTU
   512  
   513  	ASLL
   514  	ASQRTD
   515  	ASQRTF
   516  	ASRA
   517  	ASRL
   518  	AROTR
   519  	ASUB
   520  	ASUBD
   521  	ASUBF
   522  
   523  	ASUBU
   524  	ASUBW
   525  	ADBAR
   526  	ASYSCALL
   527  
   528  	ATEQ
   529  	ATNE
   530  
   531  	AWORD
   532  
   533  	AXOR
   534  
   535  	AMASKEQZ
   536  	AMASKNEZ
   537  
   538  	// 64-bit
   539  	AMOVV
   540  
   541  	ASLLV
   542  	ASRAV
   543  	ASRLV
   544  	AROTRV
   545  	ADIVV
   546  	ADIVVU
   547  
   548  	AREMV
   549  	AREMVU
   550  
   551  	AMULV
   552  	AMULVU
   553  	AMULHV
   554  	AMULHVU
   555  	AADDV
   556  	AADDVU
   557  	ASUBV
   558  	ASUBVU
   559  
   560  	// 64-bit FP
   561  	ATRUNCFV
   562  	ATRUNCDV
   563  	ATRUNCFW
   564  	ATRUNCDW
   565  
   566  	AMOVWU
   567  	AMOVFV
   568  	AMOVDV
   569  	AMOVVF
   570  	AMOVVD
   571  
   572  	// 2.2.1.8
   573  	AORN
   574  	AANDN
   575  
   576  	// 2.2.7. Atomic Memory Access Instructions
   577  	AAMSWAPB
   578  	AAMSWAPH
   579  	AAMSWAPW
   580  	AAMSWAPV
   581  	AAMCASB
   582  	AAMCASH
   583  	AAMCASW
   584  	AAMCASV
   585  	AAMADDW
   586  	AAMADDV
   587  	AAMANDW
   588  	AAMANDV
   589  	AAMORW
   590  	AAMORV
   591  	AAMXORW
   592  	AAMXORV
   593  	AAMMAXW
   594  	AAMMAXV
   595  	AAMMINW
   596  	AAMMINV
   597  	AAMMAXWU
   598  	AAMMAXVU
   599  	AAMMINWU
   600  	AAMMINVU
   601  	AAMSWAPDBB
   602  	AAMSWAPDBH
   603  	AAMSWAPDBW
   604  	AAMSWAPDBV
   605  	AAMCASDBB
   606  	AAMCASDBH
   607  	AAMCASDBW
   608  	AAMCASDBV
   609  	AAMADDDBW
   610  	AAMADDDBV
   611  	AAMANDDBW
   612  	AAMANDDBV
   613  	AAMORDBW
   614  	AAMORDBV
   615  	AAMXORDBW
   616  	AAMXORDBV
   617  	AAMMAXDBW
   618  	AAMMAXDBV
   619  	AAMMINDBW
   620  	AAMMINDBV
   621  	AAMMAXDBWU
   622  	AAMMAXDBVU
   623  	AAMMINDBWU
   624  	AAMMINDBVU
   625  
   626  	// 2.2.3.1
   627  	AEXTWB
   628  	AEXTWH
   629  
   630  	// 2.2.3.2
   631  	ACLOW
   632  	ACLOV
   633  	ACLZW
   634  	ACLZV
   635  	ACTOW
   636  	ACTOV
   637  	ACTZW
   638  	ACTZV
   639  
   640  	// 2.2.3.4
   641  	AREVBV
   642  	AREVB2W
   643  	AREVB4H
   644  	AREVB2H
   645  
   646  	// 2.2.3.5
   647  	AREVH2W
   648  	AREVHV
   649  
   650  	// 2.2.3.6
   651  	ABITREV4B
   652  	ABITREV8B
   653  
   654  	// 2.2.3.7
   655  	ABITREVW
   656  	ABITREVV
   657  
   658  	// 2.2.3.8
   659  	ABSTRINSW
   660  	ABSTRINSV
   661  
   662  	// 2.2.3.9
   663  	ABSTRPICKW
   664  	ABSTRPICKV
   665  
   666  	// 2.2.9. CRC Check Instructions
   667  	ACRCWBW
   668  	ACRCWHW
   669  	ACRCWWW
   670  	ACRCWVW
   671  	ACRCCWBW
   672  	ACRCCWHW
   673  	ACRCCWWW
   674  	ACRCCWVW
   675  
   676  	// 2.2.10. Other Miscellaneous Instructions
   677  	ARDTIMELW
   678  	ARDTIMEHW
   679  	ARDTIMED
   680  	ACPUCFG
   681  
   682  	// 3.2.1.2
   683  	AFMADDF
   684  	AFMADDD
   685  	AFMSUBF
   686  	AFMSUBD
   687  	AFNMADDF
   688  	AFNMADDD
   689  	AFNMSUBF
   690  	AFNMSUBD
   691  
   692  	// 3.2.1.3
   693  	AFMINF
   694  	AFMIND
   695  	AFMAXF
   696  	AFMAXD
   697  
   698  	// 3.2.1.4
   699  	AFMAXAF
   700  	AFMAXAD
   701  	AFMINAF
   702  	AFMINAD
   703  
   704  	// 3.2.1.7
   705  	AFCOPYSGF
   706  	AFCOPYSGD
   707  	AFSCALEBF
   708  	AFSCALEBD
   709  	AFLOGBF
   710  	AFLOGBD
   711  
   712  	// 3.2.1.8
   713  	AFCLASSF
   714  	AFCLASSD
   715  
   716  	// 3.2.3.2
   717  	AFFINTFW
   718  	AFFINTFV
   719  	AFFINTDW
   720  	AFFINTDV
   721  	AFTINTWF
   722  	AFTINTWD
   723  	AFTINTVF
   724  	AFTINTVD
   725  
   726  	// 3.2.3.3
   727  	AFTINTRPWF
   728  	AFTINTRPWD
   729  	AFTINTRPVF
   730  	AFTINTRPVD
   731  	AFTINTRMWF
   732  	AFTINTRMWD
   733  	AFTINTRMVF
   734  	AFTINTRMVD
   735  	AFTINTRZWF
   736  	AFTINTRZWD
   737  	AFTINTRZVF
   738  	AFTINTRZVD
   739  	AFTINTRNEWF
   740  	AFTINTRNEWD
   741  	AFTINTRNEVF
   742  	AFTINTRNEVD
   743  
   744  	// LSX and LASX memory access instructions
   745  	AVMOVQ
   746  	AXVMOVQ
   747  
   748  	// LSX and LASX arithmetic instructions
   749  	AVADDB
   750  	AVADDH
   751  	AVADDW
   752  	AVADDV
   753  	AVADDQ
   754  	AXVADDB
   755  	AXVADDH
   756  	AXVADDW
   757  	AXVADDV
   758  	AXVADDQ
   759  	AVSUBB
   760  	AVSUBH
   761  	AVSUBW
   762  	AVSUBV
   763  	AVSUBQ
   764  	AXVSUBB
   765  	AXVSUBH
   766  	AXVSUBW
   767  	AXVSUBV
   768  	AXVSUBQ
   769  	AVADDBU
   770  	AVADDHU
   771  	AVADDWU
   772  	AVADDVU
   773  	AVSUBBU
   774  	AVSUBHU
   775  	AVSUBWU
   776  	AVSUBVU
   777  	AXVADDBU
   778  	AXVADDHU
   779  	AXVADDWU
   780  	AXVADDVU
   781  	AXVSUBBU
   782  	AXVSUBHU
   783  	AXVSUBWU
   784  	AXVSUBVU
   785  
   786  	// LSX and LASX Bit-manipulation Instructions
   787  	AVANDB
   788  	AVORB
   789  	AVXORB
   790  	AVNORB
   791  	AXVANDB
   792  	AXVORB
   793  	AXVXORB
   794  	AXVNORB
   795  	AVANDV
   796  	AVORV
   797  	AVXORV
   798  	AVNORV
   799  	AVANDNV
   800  	AVORNV
   801  	AXVANDV
   802  	AXVORV
   803  	AXVXORV
   804  	AXVNORV
   805  	AXVANDNV
   806  	AXVORNV
   807  
   808  	AVPCNTB
   809  	AVPCNTH
   810  	AVPCNTW
   811  	AVPCNTV
   812  	AXVPCNTB
   813  	AXVPCNTH
   814  	AXVPCNTW
   815  	AXVPCNTV
   816  
   817  	// LSX and LASX integer comparison instruction
   818  	AVSEQB
   819  	AXVSEQB
   820  	AVSEQH
   821  	AXVSEQH
   822  	AVSEQW
   823  	AXVSEQW
   824  	AVSEQV
   825  	AXVSEQV
   826  
   827  	// LSX and LASX integer div and mod instructions
   828  	AVDIVB
   829  	AVDIVH
   830  	AVDIVW
   831  	AVDIVV
   832  	AVDIVBU
   833  	AVDIVHU
   834  	AVDIVWU
   835  	AVDIVVU
   836  	AVMODB
   837  	AVMODH
   838  	AVMODW
   839  	AVMODV
   840  	AVMODBU
   841  	AVMODHU
   842  	AVMODWU
   843  	AVMODVU
   844  	AXVDIVB
   845  	AXVDIVH
   846  	AXVDIVW
   847  	AXVDIVV
   848  	AXVDIVBU
   849  	AXVDIVHU
   850  	AXVDIVWU
   851  	AXVDIVVU
   852  	AXVMODB
   853  	AXVMODH
   854  	AXVMODW
   855  	AXVMODV
   856  	AXVMODBU
   857  	AXVMODHU
   858  	AXVMODWU
   859  	AXVMODVU
   860  
   861  	// LSX and LASX shift operation instructions
   862  	AVSLLB
   863  	AVSLLH
   864  	AVSLLW
   865  	AVSLLV
   866  	AVSRLB
   867  	AVSRLH
   868  	AVSRLW
   869  	AVSRLV
   870  	AVSRAB
   871  	AVSRAH
   872  	AVSRAW
   873  	AVSRAV
   874  	AVROTRB
   875  	AVROTRH
   876  	AVROTRW
   877  	AVROTRV
   878  	AXVSLLB
   879  	AXVSLLH
   880  	AXVSLLW
   881  	AXVSLLV
   882  	AXVSRLB
   883  	AXVSRLH
   884  	AXVSRLW
   885  	AXVSRLV
   886  	AXVSRAB
   887  	AXVSRAH
   888  	AXVSRAW
   889  	AXVSRAV
   890  	AXVROTRB
   891  	AXVROTRH
   892  	AXVROTRW
   893  	AXVROTRV
   894  
   895  	// LSX and LASX move and shuffle instructions
   896  	AVILVLB
   897  	AVILVLH
   898  	AVILVLW
   899  	AVILVLV
   900  	AVILVHB
   901  	AVILVHH
   902  	AVILVHW
   903  	AVILVHV
   904  	AXVILVLB
   905  	AXVILVLH
   906  	AXVILVLW
   907  	AXVILVLV
   908  	AXVILVHB
   909  	AXVILVHH
   910  	AXVILVHW
   911  	AXVILVHV
   912  
   913  	// LSX and LASX integer mul instructions
   914  	AVMULB
   915  	AVMULH
   916  	AVMULW
   917  	AVMULV
   918  	AVMUHB
   919  	AVMUHH
   920  	AVMUHW
   921  	AVMUHV
   922  	AVMUHBU
   923  	AVMUHHU
   924  	AVMUHWU
   925  	AVMUHVU
   926  	AXVMULB
   927  	AXVMULH
   928  	AXVMULW
   929  	AXVMULV
   930  	AXVMUHB
   931  	AXVMUHH
   932  	AXVMUHW
   933  	AXVMUHV
   934  	AXVMUHBU
   935  	AXVMUHHU
   936  	AXVMUHWU
   937  	AXVMUHVU
   938  
   939  	// LSX and LASX floating point instructions
   940  	AVFSQRTF
   941  	AVFSQRTD
   942  	AVFRECIPF
   943  	AVFRECIPD
   944  	AVFRSQRTF
   945  	AVFRSQRTD
   946  	AXVFSQRTF
   947  	AXVFSQRTD
   948  	AXVFRECIPF
   949  	AXVFRECIPD
   950  	AXVFRSQRTF
   951  	AXVFRSQRTD
   952  
   953  	// LSX and LASX integer neg instructions
   954  	AVNEGB
   955  	AVNEGH
   956  	AVNEGW
   957  	AVNEGV
   958  	AXVNEGB
   959  	AXVNEGH
   960  	AXVNEGW
   961  	AXVNEGV
   962  
   963  	// LSX and LASX mul instructions that operate on even or odd positions
   964  	AVMULWEVHB
   965  	AVMULWEVWH
   966  	AVMULWEVVW
   967  	AVMULWEVQV
   968  	AVMULWODHB
   969  	AVMULWODWH
   970  	AVMULWODVW
   971  	AVMULWODQV
   972  	AVMULWEVHBU
   973  	AVMULWEVWHU
   974  	AVMULWEVVWU
   975  	AVMULWEVQVU
   976  	AVMULWODHBU
   977  	AVMULWODWHU
   978  	AVMULWODVWU
   979  	AVMULWODQVU
   980  	AXVMULWEVHB
   981  	AXVMULWEVWH
   982  	AXVMULWEVVW
   983  	AXVMULWEVQV
   984  	AXVMULWODHB
   985  	AXVMULWODWH
   986  	AXVMULWODVW
   987  	AXVMULWODQV
   988  	AXVMULWEVHBU
   989  	AXVMULWEVWHU
   990  	AXVMULWEVVWU
   991  	AXVMULWEVQVU
   992  	AXVMULWODHBU
   993  	AXVMULWODWHU
   994  	AXVMULWODVWU
   995  	AXVMULWODQVU
   996  	AVMULWEVHBUB
   997  	AVMULWEVWHUH
   998  	AVMULWEVVWUW
   999  	AVMULWEVQVUV
  1000  	AVMULWODHBUB
  1001  	AVMULWODWHUH
  1002  	AVMULWODVWUW
  1003  	AVMULWODQVUV
  1004  	AXVMULWEVHBUB
  1005  	AXVMULWEVWHUH
  1006  	AXVMULWEVVWUW
  1007  	AXVMULWEVQVUV
  1008  	AXVMULWODHBUB
  1009  	AXVMULWODWHUH
  1010  	AXVMULWODVWUW
  1011  	AXVMULWODQVUV
  1012  
  1013  	AVSHUF4IB
  1014  	AVSHUF4IH
  1015  	AVSHUF4IW
  1016  	AVSHUF4IV
  1017  	AXVSHUF4IB
  1018  	AXVSHUF4IH
  1019  	AXVSHUF4IW
  1020  	AXVSHUF4IV
  1021  
  1022  	AVSETEQV
  1023  	AVSETNEV
  1024  	AVSETANYEQB
  1025  	AVSETANYEQH
  1026  	AVSETANYEQW
  1027  	AVSETANYEQV
  1028  	AVSETALLNEB
  1029  	AVSETALLNEH
  1030  	AVSETALLNEW
  1031  	AVSETALLNEV
  1032  	AXVSETEQV
  1033  	AXVSETNEV
  1034  	AXVSETANYEQB
  1035  	AXVSETANYEQH
  1036  	AXVSETANYEQW
  1037  	AXVSETANYEQV
  1038  	AXVSETALLNEB
  1039  	AXVSETALLNEH
  1040  	AXVSETALLNEW
  1041  	AXVSETALLNEV
  1042  
  1043  	ALAST
  1044  
  1045  	// aliases
  1046  	AJMP = obj.AJMP
  1047  	AJAL = obj.ACALL
  1048  	ARET = obj.ARET
  1049  )
  1050  
  1051  func init() {
  1052  	// The asm encoder generally assumes that the lowest 5 bits of the
  1053  	// REG_XX constants match the machine instruction encoding, i.e.
  1054  	// the lowest 5 bits is the register number.
  1055  	// Check this here.
  1056  	if REG_R0%32 != 0 {
  1057  		panic("REG_R0 is not a multiple of 32")
  1058  	}
  1059  	if REG_F0%32 != 0 {
  1060  		panic("REG_F0 is not a multiple of 32")
  1061  	}
  1062  	if REG_FCSR0%32 != 0 {
  1063  		panic("REG_FCSR0 is not a multiple of 32")
  1064  	}
  1065  	if REG_FCC0%32 != 0 {
  1066  		panic("REG_FCC0 is not a multiple of 32")
  1067  	}
  1068  	if REG_V0%32 != 0 {
  1069  		panic("REG_V0 is not a multiple of 32")
  1070  	}
  1071  	if REG_X0%32 != 0 {
  1072  		panic("REG_X0 is not a multiple of 32")
  1073  	}
  1074  }
  1075
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