1 // Copyright 2015 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 // Lowering arithmetic
6 (Add(64|32|16|8) ...) => (ADD(Q|L|L|L) ...)
7 (AddPtr ...) => (ADDQ ...)
8 (Add(32|64)F ...) => (ADDS(S|D) ...)
9
10 (Sub(64|32|16|8) ...) => (SUB(Q|L|L|L) ...)
11 (SubPtr ...) => (SUBQ ...)
12 (Sub(32|64)F ...) => (SUBS(S|D) ...)
13
14 (Mul(64|32|16|8) ...) => (MUL(Q|L|L|L) ...)
15 (Mul(32|64)F ...) => (MULS(S|D) ...)
16
17 (Select0 (Mul64uover x y)) => (Select0 <typ.UInt64> (MULQU x y))
18 (Select0 (Mul32uover x y)) => (Select0 <typ.UInt32> (MULLU x y))
19 (Select1 (Mul(64|32)uover x y)) => (SETO (Select1 <types.TypeFlags> (MUL(Q|L)U x y)))
20
21 (Hmul(64|32) ...) => (HMUL(Q|L) ...)
22 (Hmul(64|32)u ...) => (HMUL(Q|L)U ...)
23
24 (Div(64|32|16) [a] x y) => (Select0 (DIV(Q|L|W) [a] x y))
25 (Div8 x y) => (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
26 (Div(64|32|16)u x y) => (Select0 (DIV(Q|L|W)U x y))
27 (Div8u x y) => (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
28 (Div(32|64)F ...) => (DIVS(S|D) ...)
29
30 (Select0 (Add64carry x y c)) => (Select0 (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
31 (Select1 (Add64carry x y c)) => (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
32 (Select0 (Sub64borrow x y c)) => (Select0 (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
33 (Select1 (Sub64borrow x y c)) => (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
34 // Optimize ADCQ and friends
35 (ADCQ x (MOVQconst [c]) carry) && ssa.Is32Bit(c) => (ADCQconst x [int32(c)] carry)
36 (ADCQ x y (FlagEQ)) => (ADDQcarry x y)
37 (ADCQconst x [c] (FlagEQ)) => (ADDQconstcarry x [c])
38 (ADDQcarry x (MOVQconst [c])) && ssa.Is32Bit(c) => (ADDQconstcarry x [int32(c)])
39 (SBBQ x (MOVQconst [c]) borrow) && ssa.Is32Bit(c) => (SBBQconst x [int32(c)] borrow)
40 (SBBQ x y (FlagEQ)) => (SUBQborrow x y)
41 (SBBQconst x [c] (FlagEQ)) => (SUBQconstborrow x [c])
42 (SUBQborrow x (MOVQconst [c])) && ssa.Is32Bit(c) => (SUBQconstborrow x [int32(c)])
43 (Select1 (NEGLflags (MOVQconst [0]))) => (FlagEQ)
44 (Select1 (NEGLflags (MOVBQZX (SETB x)))) => x
45 // Absorb InvertFlags into ADCQ/SBBQ: CF(InvertFlags(f)) = SETA(f), so
46 // re-materialize the carry/borrow through the SETA+NEGLflags path.
47 (ADCQ x y (InvertFlags f)) => (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
48 (ADCQconst x [c] (InvertFlags f)) => (ADCQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
49 (SBBQ x y (InvertFlags f)) => (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
50 (SBBQconst x [c] (InvertFlags f)) => (SBBQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
51 // ADDQ/SUBQ an from a carry flag into ADCQ/SBBQ
52 // TODO: maybe add ADCL and SBBL ?
53 (ADDQ x (MOVBQZX (SETB flags))) => (Select0 (ADCQconst [0] x flags))
54 (SUBQ x (MOVBQZX (SETB flags))) => (Select0 (SBBQconst [0] x flags))
55
56 (Mul64uhilo x y) && buildcfg.GOAMD64 >= 3 => (MULXQ x y)
57 (Mul64uhilo x y) && buildcfg.GOAMD64 < 3 => (MULQU2 x y)
58 (Div128u ...) => (DIVQU2 ...)
59
60 (Avg64u ...) => (AVGQU ...)
61
62 (Mod(64|32|16) [a] x y) => (Select1 (DIV(Q|L|W) [a] x y))
63 (Mod8 x y) => (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
64 (Mod(64|32|16)u x y) => (Select1 (DIV(Q|L|W)U x y))
65 (Mod8u x y) => (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
66
67 (And(64|32|16|8) ...) => (AND(Q|L|L|L) ...)
68 (Or(64|32|16|8) ...) => (OR(Q|L|L|L) ...)
69 (Xor(64|32|16|8) ...) => (XOR(Q|L|L|L) ...)
70 (Com(64|32|16|8) ...) => (NOT(Q|L|L|L) ...)
71
72 (Neg(64|32|16|8) ...) => (NEG(Q|L|L|L) ...)
73 (Neg32F x) => (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
74 (Neg64F x) => (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
75
76 // Lowering boolean ops
77 (AndB ...) => (ANDL ...)
78 (OrB ...) => (ORL ...)
79 (Not x) => (XORLconst [1] x)
80
81 // Lowering pointer arithmetic
82 (OffPtr [off] ptr) && ssa.Is32Bit(off) => (ADDQconst [int32(off)] ptr)
83 (OffPtr [off] ptr) => (ADDQ (MOVQconst [off]) ptr)
84
85 // Lowering other arithmetic
86 (Ctz64 x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
87 (Ctz32 x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
88 (Ctz64 <t> x) && buildcfg.GOAMD64 < 3 => (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
89 (Ctz32 x) && buildcfg.GOAMD64 < 3 => (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
90 (Ctz16 x) => (BSFL (ORLconst <typ.UInt32> [1<<16] x))
91 (Ctz8 x) => (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
92
93 (Ctz64NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTQ x)
94 (Ctz32NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
95 (Ctz16NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
96 (Ctz8NonZero x) && buildcfg.GOAMD64 >= 3 => (TZCNTL x)
97 (Ctz64NonZero x) && buildcfg.GOAMD64 < 3 => (Select0 (BSFQ x))
98 (Ctz32NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
99 (Ctz16NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
100 (Ctz8NonZero x) && buildcfg.GOAMD64 < 3 => (BSFL x)
101
102 // BitLen64 of a 64 bit value x requires checking whether x == 0, since BSRQ is undefined when x == 0.
103 // However, for zero-extended values, we can cheat a bit, and calculate
104 // BSR(x<<1 + 1), which is guaranteed to be non-zero, and which conveniently
105 // places the index of the highest set bit where we want it.
106 // For GOAMD64>=3, BitLen can be calculated by OperandSize - LZCNT(x).
107 (BitLen64 <t> x) && buildcfg.GOAMD64 < 3 => (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
108 (BitLen32 x) && buildcfg.GOAMD64 < 3 => (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
109 (BitLen16 x) && buildcfg.GOAMD64 < 3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
110 (BitLen8 x) && buildcfg.GOAMD64 < 3 => (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
111 (BitLen64 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
112 // Use 64-bit version to allow const-fold remove unnecessary arithmetic.
113 (BitLen32 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
114 (BitLen16 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
115 (BitLen8 <t> x) && buildcfg.GOAMD64 >= 3 => (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))
116
117 (Bswap(64|32) ...) => (BSWAP(Q|L) ...)
118 (Bswap16 x) => (ROLWconst [8] x)
119
120 (PopCount(64|32) ...) => (POPCNT(Q|L) ...)
121 (PopCount16 x) => (POPCNTL (MOVWQZX <typ.UInt32> x))
122 (PopCount8 x) => (POPCNTL (MOVBQZX <typ.UInt32> x))
123
124 (Sqrt ...) => (SQRTSD ...)
125 (Sqrt32 ...) => (SQRTSS ...)
126
127 (RoundToEven x) => (ROUNDSD [0] x)
128 (Floor x) => (ROUNDSD [1] x)
129 (Ceil x) => (ROUNDSD [2] x)
130 (Trunc x) => (ROUNDSD [3] x)
131
132 (CVTSD2SS (ROUNDSD [c] (CVTSS2SD x))) => (ROUNDSS [c] x)
133
134 (FMA x y z) => (VFMADD231SD z x y)
135
136 // Lowering extension
137 // Note: we always extend to 64 bits even though some ops don't need that many result bits.
138 (SignExt8to16 ...) => (MOVBQSX ...)
139 (SignExt8to32 ...) => (MOVBQSX ...)
140 (SignExt8to64 ...) => (MOVBQSX ...)
141 (SignExt16to32 ...) => (MOVWQSX ...)
142 (SignExt16to64 ...) => (MOVWQSX ...)
143 (SignExt32to64 ...) => (MOVLQSX ...)
144
145 (ZeroExt8to16 ...) => (MOVBQZX ...)
146 (ZeroExt8to32 ...) => (MOVBQZX ...)
147 (ZeroExt8to64 ...) => (MOVBQZX ...)
148 (ZeroExt16to32 ...) => (MOVWQZX ...)
149 (ZeroExt16to64 ...) => (MOVWQZX ...)
150 (ZeroExt32to64 ...) => (MOVLQZX ...)
151
152 (Slicemask <t> x) => (SARQconst (NEGQ <t> x) [63])
153
154 (SpectreIndex <t> x y) => (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
155 (SpectreSliceIndex <t> x y) => (CMOVQHI x (MOVQconst [0]) (CMPQ x y))
156
157 // Lowering truncation
158 // Because we ignore high parts of registers, truncates are just copies.
159 (Trunc16to8 ...) => (Copy ...)
160 (Trunc32to8 ...) => (Copy ...)
161 (Trunc32to16 ...) => (Copy ...)
162 (Trunc64to8 ...) => (Copy ...)
163 (Trunc64to16 ...) => (Copy ...)
164 (Trunc64to32 ...) => (Copy ...)
165
166 // Lowering float <-> int
167 (Cvt32to32F ...) => (CVTSL2SS ...)
168 (Cvt32to64F ...) => (CVTSL2SD ...)
169 (Cvt64to32F ...) => (CVTSQ2SS ...)
170 (Cvt64to64F ...) => (CVTSQ2SD ...)
171
172 // Float, to int.
173 // To make AMD64 "overflow" return max positive instead of max negative, compute
174 // y and not x, smear the sign bit, and xor.
175 (Cvt32Fto32 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSS2SL <t> x) (NOTL <typ.Int32> (MOVLf2i x)))))
176 (Cvt64Fto32 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSD2SL <t> x) (NOTL <typ.Int32> (MOVLf2i (CVTSD2SS <typ.Float32> x))))))
177
178 (Cvt32Fto64 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSS2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i (CVTSS2SD <typ.Float64> x))) )))
179 (Cvt64Fto64 <t> x) && base.ConvertHash.MatchPos(v.Pos, nil) => (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSD2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i x)))))
180
181 (Cvt32Fto32 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSS2SL <t> x)
182 (Cvt32Fto64 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSS2SQ <t> x)
183 (Cvt64Fto32 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSD2SL <t> x)
184 (Cvt64Fto64 <t> x) && !base.ConvertHash.MatchPos(v.Pos, nil) => (CVTTSD2SQ <t> x)
185
186 (Cvt32Fto64F ...) => (CVTSS2SD ...)
187 (Cvt64Fto32F ...) => (CVTSD2SS ...)
188
189 (Round(32|64)F ...) => (LoweredRound(32|64)F ...)
190
191 // Floating-point min is tricky, as the hardware op isn't right for various special
192 // cases (-0 and NaN). We use two hardware ops organized just right to make the
193 // result come out how we want it. See https://github.com/golang/go/issues/59488#issuecomment-1553493207
194 // (although that comment isn't exactly right, as the value overwritten is not simulated correctly).
195 // t1 = MINSD x, y => incorrect if x==NaN or x==-0,y==+0
196 // t2 = MINSD t1, x => fixes x==NaN case
197 // res = POR t1, t2 => fixes x==-0,y==+0 case
198 // Note that this trick depends on the special property that (NaN OR x) produces a NaN (although
199 // it might not produce the same NaN as the input).
200 (Min(64|32)F <t> x y) => (POR (MINS(D|S) <t> (MINS(D|S) <t> x y) x) (MINS(D|S) <t> x y))
201 // Floating-point max is even trickier. Punt to using min instead.
202 // max(x,y) == -min(-x,-y)
203 (Max(64|32)F <t> x y) => (Neg(64|32)F <t> (Min(64|32)F <t> (Neg(64|32)F <t> x) (Neg(64|32)F <t> y)))
204
205 (CvtBoolToUint8 ...) => (Copy ...)
206
207 // Lowering shifts
208 // Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
209 // result = (arg << shift) & (shift >= argbits ? 0 : 0xffffffffffffffff)
210 (Lsh64x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
211 (Lsh32x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
212 (Lsh16x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
213 (Lsh8x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
214
215 (Lsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLQ x y)
216 (Lsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLL x y)
217 (Lsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLL x y)
218 (Lsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHLL x y)
219
220 (Rsh64Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMP(Q|L|W|B)const y [64])))
221 (Rsh32Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [32])))
222 (Rsh16Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [16])))
223 (Rsh8Ux(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMP(Q|L|W|B)const y [8])))
224
225 (Rsh64Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRQ x y)
226 (Rsh32Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRL x y)
227 (Rsh16Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRW x y)
228 (Rsh8Ux(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SHRB x y)
229
230 // Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
231 // We implement this by setting the shift value to -1 (all ones) if the shift value is >= width.
232 (Rsh64x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARQ <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [64])))))
233 (Rsh32x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARL <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [32])))))
234 (Rsh16x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARW <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [16])))))
235 (Rsh8x(64|32|16|8) <t> x y) && !ssa.ShiftIsBounded(v) => (SARB <t> x (OR(Q|L|L|L) <y.Type> y (NOT(Q|L|L|L) <y.Type> (SBB(Q|L|L|L)carrymask <y.Type> (CMP(Q|L|W|B)const y [8])))))
236
237 (Rsh64x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARQ x y)
238 (Rsh32x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARL x y)
239 (Rsh16x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARW x y)
240 (Rsh8x(64|32|16|8) x y) && ssa.ShiftIsBounded(v) => (SARB x y)
241
242 // Lowering integer comparisons
243 (Less(64|32|16|8) x y) => (SETL (CMP(Q|L|W|B) x y))
244 (Less(64|32|16|8)U x y) => (SETB (CMP(Q|L|W|B) x y))
245 (Leq(64|32|16|8) x y) => (SETLE (CMP(Q|L|W|B) x y))
246 (Leq(64|32|16|8)U x y) => (SETBE (CMP(Q|L|W|B) x y))
247 (Eq(Ptr|64|32|16|8|B) x y) => (SETEQ (CMP(Q|Q|L|W|B|B) x y))
248 (Neq(Ptr|64|32|16|8|B) x y) => (SETNE (CMP(Q|Q|L|W|B|B) x y))
249
250 // Lowering floating point comparisons
251 // Note Go assembler gets UCOMISx operand order wrong, but it is right here
252 // and the operands are reversed when generating assembly language.
253 (Eq(32|64)F x y) => (SETEQF (UCOMIS(S|D) x y))
254 (Neq(32|64)F x y) => (SETNEF (UCOMIS(S|D) x y))
255 // Use SETGF/SETGEF with reversed operands to dodge NaN case.
256 (Less(32|64)F x y) => (SETGF (UCOMIS(S|D) y x))
257 (Leq(32|64)F x y) => (SETGEF (UCOMIS(S|D) y x))
258
259 // Lowering loads
260 (Load <t> ptr mem) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t)) => (MOVQload ptr mem)
261 (Load <t> ptr mem) && ssa.Is32BitInt(t) => (MOVLload ptr mem)
262 (Load <t> ptr mem) && ssa.Is16BitInt(t) => (MOVWload ptr mem)
263 (Load <t> ptr mem) && (t.IsBoolean() || ssa.Is8BitInt(t)) => (MOVBload ptr mem)
264 (Load <t> ptr mem) && ssa.Is32BitFloat(t) => (MOVSSload ptr mem)
265 (Load <t> ptr mem) && ssa.Is64BitFloat(t) => (MOVSDload ptr mem)
266
267 // Lowering stores
268 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVSDstore ptr val mem)
269 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVSSstore ptr val mem)
270 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVQstore ptr val mem)
271 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVLstore ptr val mem)
272 (Store {t} ptr val mem) && t.Size() == 2 => (MOVWstore ptr val mem)
273 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
274
275 // Lowering moves
276 (Move [0] _ _ mem) => mem
277 (Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
278 (Move [2] dst src mem) => (MOVWstore dst (MOVWload src mem) mem)
279 (Move [4] dst src mem) => (MOVLstore dst (MOVLload src mem) mem)
280 (Move [8] dst src mem) => (MOVQstore dst (MOVQload src mem) mem)
281 (Move [16] dst src mem) => (MOVOstore dst (MOVOload src mem) mem)
282
283 (Move [3] dst src mem) =>
284 (MOVBstore [2] dst (MOVBload [2] src mem)
285 (MOVWstore dst (MOVWload src mem) mem))
286 (Move [5] dst src mem) =>
287 (MOVBstore [4] dst (MOVBload [4] src mem)
288 (MOVLstore dst (MOVLload src mem) mem))
289 (Move [6] dst src mem) =>
290 (MOVWstore [4] dst (MOVWload [4] src mem)
291 (MOVLstore dst (MOVLload src mem) mem))
292 (Move [7] dst src mem) =>
293 (MOVLstore [3] dst (MOVLload [3] src mem)
294 (MOVLstore dst (MOVLload src mem) mem))
295 (Move [9] dst src mem) =>
296 (MOVBstore [8] dst (MOVBload [8] src mem)
297 (MOVQstore dst (MOVQload src mem) mem))
298 (Move [10] dst src mem) =>
299 (MOVWstore [8] dst (MOVWload [8] src mem)
300 (MOVQstore dst (MOVQload src mem) mem))
301 (Move [11] dst src mem) =>
302 (MOVLstore [7] dst (MOVLload [7] src mem)
303 (MOVQstore dst (MOVQload src mem) mem))
304 (Move [12] dst src mem) =>
305 (MOVLstore [8] dst (MOVLload [8] src mem)
306 (MOVQstore dst (MOVQload src mem) mem))
307 (Move [s] dst src mem) && s >= 13 && s <= 15 =>
308 (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem)
309 (MOVQstore dst (MOVQload src mem) mem))
310
311 // Copying up to 192 bytes uses straightline code.
312 (Move [s] dst src mem) && s > 16 && s < 192 && ssa.LogLargeCopyValue(v, s) => (LoweredMove [s] dst src mem)
313
314 // Copying up to ~1KB uses a small loop.
315 (Move [s] dst src mem) && s >= 192 && s <= ssa.RepMoveThreshold && ssa.LogLargeCopyValue(v, s) => (LoweredMoveLoop [s] dst src mem)
316
317 // Large copying uses REP MOVSQ.
318 (Move [s] dst src mem) && s > ssa.RepMoveThreshold && s%8 != 0 =>
319 (Move [s-s%8]
320 (OffPtr <dst.Type> dst [s%8])
321 (OffPtr <src.Type> src [s%8])
322 (MOVQstore dst (MOVQload src mem) mem))
323 (Move [s] dst src mem) && s > ssa.RepMoveThreshold && s%8 == 0 && ssa.LogLargeCopyValue(v, s) =>
324 (REPMOVSQ dst src (MOVQconst [s/8]) mem)
325
326 // Lowering Zero instructions
327 (Zero [0] _ mem) => mem
328 (Zero [1] destptr mem) => (MOVBstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
329 (Zero [2] destptr mem) => (MOVWstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
330 (Zero [4] destptr mem) => (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
331 (Zero [8] destptr mem) => (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
332
333 (Zero [3] destptr mem) =>
334 (MOVBstoreconst [ssa.MakeValAndOff(0,2)] destptr
335 (MOVWstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
336 (Zero [5] destptr mem) =>
337 (MOVBstoreconst [ssa.MakeValAndOff(0,4)] destptr
338 (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
339 (Zero [6] destptr mem) =>
340 (MOVWstoreconst [ssa.MakeValAndOff(0,4)] destptr
341 (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
342 (Zero [7] destptr mem) =>
343 (MOVLstoreconst [ssa.MakeValAndOff(0,3)] destptr
344 (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
345
346 // Zero small numbers of words directly.
347 (Zero [9] destptr mem) =>
348 (MOVBstoreconst [ssa.MakeValAndOff(0,8)] destptr
349 (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
350
351 (Zero [10] destptr mem) =>
352 (MOVWstoreconst [ssa.MakeValAndOff(0,8)] destptr
353 (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
354
355 (Zero [11] destptr mem) =>
356 (MOVLstoreconst [ssa.MakeValAndOff(0,7)] destptr
357 (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
358
359 (Zero [12] destptr mem) =>
360 (MOVLstoreconst [ssa.MakeValAndOff(0,8)] destptr
361 (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
362
363 (Zero [s] destptr mem) && s > 12 && s < 16 =>
364 (MOVQstoreconst [ssa.MakeValAndOff(0,int32(s-8))] destptr
365 (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
366
367 // Zeroing up to 192 bytes uses straightline code.
368 (Zero [s] destptr mem) && s >= 16 && s < 192 => (LoweredZero [s] destptr mem)
369
370 // Zeroing up to ~1KB uses a small loop.
371 (Zero [s] destptr mem) && s >= 192 && s <= ssa.RepZeroThreshold => (LoweredZeroLoop [s] destptr mem)
372
373 // Large zeroing uses REP STOSQ.
374 (Zero [s] destptr mem) && s > ssa.RepZeroThreshold && s%8 != 0 =>
375 (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8])
376 (MOVOstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
377 (Zero [s] destptr mem) && s > ssa.RepZeroThreshold && s%8 == 0 =>
378 (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)
379
380 // Lowering constants
381 (Const8 [c]) => (MOVLconst [int32(c)])
382 (Const16 [c]) => (MOVLconst [int32(c)])
383 (Const32 ...) => (MOVLconst ...)
384 (Const64 ...) => (MOVQconst ...)
385 (Const32F ...) => (MOVSSconst ...)
386 (Const64F ...) => (MOVSDconst ...)
387 (ConstNil ) => (MOVQconst [0])
388 (ConstBool [c]) => (MOVLconst [ssa.B2i32(c)])
389
390 // Lowering calls
391 (StaticCall ...) => (CALLstatic ...)
392 (ClosureCall ...) => (CALLclosure ...)
393 (InterCall ...) => (CALLinter ...)
394 (TailCall ...) => (CALLtail ...)
395 (TailCallInter ...) => (CALLtailinter ...)
396
397 // Lowering conditional moves
398 // If the condition is a SETxx, we can just run a CMOV from the comparison that was
399 // setting the flags.
400 // Legend: HI=unsigned ABOVE, CS=unsigned BELOW, CC=unsigned ABOVE EQUAL, LS=unsigned BELOW EQUAL
401 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
402 => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
403 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && ssa.Is32BitInt(t)
404 => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
405 (CondSelect <t> x y (SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) cond)) && ssa.Is16BitInt(t)
406 => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) y x cond)
407
408 // Float min/max comparison-select idioms lower to a single instruction.
409 // These ops carry their semantics directly (no embedded comparison), so the
410 // lowering always triggers.
411 (Min64FSel ...) => (MINSD ...)
412 (Min32FSel ...) => (MINSS ...)
413 (Max64FSel ...) => (MAXSD ...)
414 (Max32FSel ...) => (MAXSS ...)
415
416 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
417 => (CMOVQNE y x (CMPQconst [0] check))
418 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is32BitInt(t)
419 => (CMOVLNE y x (CMPQconst [0] check))
420 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is16BitInt(t)
421 => (CMOVWNE y x (CMPQconst [0] check))
422 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
423 => (CMOVQNE y x (CMPLconst [0] check))
424 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is32BitInt(t)
425 => (CMOVLNE y x (CMPLconst [0] check))
426 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is16BitInt(t)
427 => (CMOVWNE y x (CMPLconst [0] check))
428 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
429 => (CMOVQNE y x (CMPWconst [0] check))
430 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is32BitInt(t)
431 => (CMOVLNE y x (CMPWconst [0] check))
432 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is16BitInt(t)
433 => (CMOVWNE y x (CMPWconst [0] check))
434 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
435 => (CMOVQNE y x (CMPBconst [0] check))
436 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is32BitInt(t)
437 => (CMOVLNE y x (CMPBconst [0] check))
438 (CondSelect <t> x y check) && !check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is16BitInt(t)
439 => (CMOVWNE y x (CMPBconst [0] check))
440
441 // Absorb InvertFlags
442 (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
443 => (CMOVQ(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
444 (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
445 => (CMOVL(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
446 (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS) x y (InvertFlags cond))
447 => (CMOVW(EQ|NE|GT|LT|GE|LE|CS|HI|LS|CC) x y cond)
448
449 // Absorb constants generated during lower
450 (CMOV(QEQ|QLE|QGE|QCC|QLS|LEQ|LLE|LGE|LCC|LLS|WEQ|WLE|WGE|WCC|WLS) _ x (FlagEQ)) => x
451 (CMOV(QNE|QLT|QGT|QCS|QHI|LNE|LLT|LGT|LCS|LHI|WNE|WLT|WGT|WCS|WHI) y _ (FlagEQ)) => y
452 (CMOV(QNE|QGT|QGE|QHI|QCC|LNE|LGT|LGE|LHI|LCC|WNE|WGT|WGE|WHI|WCC) _ x (FlagGT_UGT)) => x
453 (CMOV(QEQ|QLE|QLT|QLS|QCS|LEQ|LLE|LLT|LLS|LCS|WEQ|WLE|WLT|WLS|WCS) y _ (FlagGT_UGT)) => y
454 (CMOV(QNE|QGT|QGE|QLS|QCS|LNE|LGT|LGE|LLS|LCS|WNE|WGT|WGE|WLS|WCS) _ x (FlagGT_ULT)) => x
455 (CMOV(QEQ|QLE|QLT|QHI|QCC|LEQ|LLE|LLT|LHI|LCC|WEQ|WLE|WLT|WHI|WCC) y _ (FlagGT_ULT)) => y
456 (CMOV(QNE|QLT|QLE|QCS|QLS|LNE|LLT|LLE|LCS|LLS|WNE|WLT|WLE|WCS|WLS) _ x (FlagLT_ULT)) => x
457 (CMOV(QEQ|QGT|QGE|QHI|QCC|LEQ|LGT|LGE|LHI|LCC|WEQ|WGT|WGE|WHI|WCC) y _ (FlagLT_ULT)) => y
458 (CMOV(QNE|QLT|QLE|QHI|QCC|LNE|LLT|LLE|LHI|LCC|WNE|WLT|WLE|WHI|WCC) _ x (FlagLT_UGT)) => x
459 (CMOV(QEQ|QGT|QGE|QCS|QLS|LEQ|LGT|LGE|LCS|LLS|WEQ|WGT|WGE|WCS|WLS) y _ (FlagLT_UGT)) => y
460
461 // Miscellaneous
462 (IsNonNil p) => (SETNE (TESTQ p p))
463 (IsInBounds idx len) => (SETB (CMPQ idx len))
464 (IsSliceInBounds idx len) => (SETBE (CMPQ idx len))
465 (NilCheck ...) => (LoweredNilCheck ...)
466 (GetG mem) && v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal => (LoweredGetG mem) // only lower in old ABI. in new ABI we have a G register.
467 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
468 (GetCallerPC ...) => (LoweredGetCallerPC ...)
469 (GetCallerSP ...) => (LoweredGetCallerSP ...)
470
471 (HasCPUFeature {s}) => (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
472 (Addr {sym} base) => (LEAQ {sym} base)
473 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (LEAQ {sym} (SPanchored base mem))
474 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (LEAQ {sym} base)
475
476 (MOVBstore [off] {sym} ptr y:(SETL x) mem) && y.Uses == 1 => (SETLstore [off] {sym} ptr x mem)
477 (MOVBstore [off] {sym} ptr y:(SETLE x) mem) && y.Uses == 1 => (SETLEstore [off] {sym} ptr x mem)
478 (MOVBstore [off] {sym} ptr y:(SETG x) mem) && y.Uses == 1 => (SETGstore [off] {sym} ptr x mem)
479 (MOVBstore [off] {sym} ptr y:(SETGE x) mem) && y.Uses == 1 => (SETGEstore [off] {sym} ptr x mem)
480 (MOVBstore [off] {sym} ptr y:(SETEQ x) mem) && y.Uses == 1 => (SETEQstore [off] {sym} ptr x mem)
481 (MOVBstore [off] {sym} ptr y:(SETNE x) mem) && y.Uses == 1 => (SETNEstore [off] {sym} ptr x mem)
482 (MOVBstore [off] {sym} ptr y:(SETB x) mem) && y.Uses == 1 => (SETBstore [off] {sym} ptr x mem)
483 (MOVBstore [off] {sym} ptr y:(SETBE x) mem) && y.Uses == 1 => (SETBEstore [off] {sym} ptr x mem)
484 (MOVBstore [off] {sym} ptr y:(SETA x) mem) && y.Uses == 1 => (SETAstore [off] {sym} ptr x mem)
485 (MOVBstore [off] {sym} ptr y:(SETAE x) mem) && y.Uses == 1 => (SETAEstore [off] {sym} ptr x mem)
486
487 // block rewrites
488 (If (SETL cmp) yes no) => (LT cmp yes no)
489 (If (SETLE cmp) yes no) => (LE cmp yes no)
490 (If (SETG cmp) yes no) => (GT cmp yes no)
491 (If (SETGE cmp) yes no) => (GE cmp yes no)
492 (If (SETEQ cmp) yes no) => (EQ cmp yes no)
493 (If (SETNE cmp) yes no) => (NE cmp yes no)
494 (If (SETB cmp) yes no) => (ULT cmp yes no)
495 (If (SETBE cmp) yes no) => (ULE cmp yes no)
496 (If (SETA cmp) yes no) => (UGT cmp yes no)
497 (If (SETAE cmp) yes no) => (UGE cmp yes no)
498 (If (SETO cmp) yes no) => (OS cmp yes no)
499
500 // Special case for floating point - LF/LEF not generated
501 (If (SETGF cmp) yes no) => (UGT cmp yes no)
502 (If (SETGEF cmp) yes no) => (UGE cmp yes no)
503 (If (SETEQF cmp) yes no) => (EQF cmp yes no)
504 (If (SETNEF cmp) yes no) => (NEF cmp yes no)
505
506 (If cond yes no) => (NE (TESTB cond cond) yes no)
507
508 (JumpTable idx) => (JUMPTABLE {ssa.MakeJumpTableSym(b)} idx (LEAQ <typ.Uintptr> {ssa.MakeJumpTableSym(b)} (SB)))
509
510 // Atomic loads. Other than preserving their ordering with respect to other loads, nothing special here.
511 (AtomicLoad8 ptr mem) => (MOVBatomicload ptr mem)
512 (AtomicLoad32 ptr mem) => (MOVLatomicload ptr mem)
513 (AtomicLoad64 ptr mem) => (MOVQatomicload ptr mem)
514 (AtomicLoadPtr ptr mem) => (MOVQatomicload ptr mem)
515
516 // Atomic stores. We use XCHG to prevent the hardware reordering a subsequent load.
517 // TODO: most runtime uses of atomic stores don't need that property. Use normal stores for those?
518 (AtomicStore8 ptr val mem) => (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
519 (AtomicStore32 ptr val mem) => (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
520 (AtomicStore64 ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
521 (AtomicStorePtrNoWB ptr val mem) => (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))
522
523 // Atomic exchanges.
524 (AtomicExchange8 ptr val mem) => (XCHGB val ptr mem)
525 (AtomicExchange32 ptr val mem) => (XCHGL val ptr mem)
526 (AtomicExchange64 ptr val mem) => (XCHGQ val ptr mem)
527
528 // Atomic adds.
529 (AtomicAdd32 ptr val mem) => (AddTupleFirst32 val (XADDLlock val ptr mem))
530 (AtomicAdd64 ptr val mem) => (AddTupleFirst64 val (XADDQlock val ptr mem))
531 (Select0 <t> (AddTupleFirst32 val tuple)) => (ADDL val (Select0 <t> tuple))
532 (Select1 (AddTupleFirst32 _ tuple)) => (Select1 tuple)
533 (Select0 <t> (AddTupleFirst64 val tuple)) => (ADDQ val (Select0 <t> tuple))
534 (Select1 (AddTupleFirst64 _ tuple)) => (Select1 tuple)
535
536 (Select1 xadd:(XADDLlock [off] {sym} val ptr mem)) && xadd.Uses == 1 && ssa.Clobber(xadd) => (ADDLlock [off] {sym} ptr val mem)
537 (Select1 xadd:(XADDQlock [off] {sym} val ptr mem)) && xadd.Uses == 1 && ssa.Clobber(xadd) => (ADDQlock [off] {sym} ptr val mem)
538 // FIXME: remove when we teach rewrite to remove dead values
539 (AddTupleFirst32 _ _) && v.Uses == 0 => (Invalid)
540 (AddTupleFirst64 _ _) && v.Uses == 0 => (Invalid)
541
542 // Atomic subtracts.
543 (ADDLlock [off] {sym} ptr n:(NEGL val) mem) && n.Uses == 1 => (SUBLlock [off] {sym} ptr val mem)
544 (ADDQlock [off] {sym} ptr n:(NEGQ val) mem) && n.Uses == 1 => (SUBQlock [off] {sym} ptr val mem)
545
546 // Atomic inc and dec.
547 (ADDLlock [off] {sym} ptr (MOVLconst [1]) mem) => (INCLlock [off] {sym} ptr mem)
548 (ADDQlock [off] {sym} ptr (MOVQconst [1]) mem) => (INCQlock [off] {sym} ptr mem)
549 (ADDLlock [off] {sym} ptr (MOVLconst [-1]) mem) => (DECLlock [off] {sym} ptr mem)
550 (ADDQlock [off] {sym} ptr (MOVQconst [-1]) mem) => (DECQlock [off] {sym} ptr mem)
551
552 // Atomic compare and swap.
553 (AtomicCompareAndSwap32 ptr old new_ mem) => (CMPXCHGLlock ptr old new_ mem)
554 (AtomicCompareAndSwap64 ptr old new_ mem) => (CMPXCHGQlock ptr old new_ mem)
555
556 // Atomic memory logical operations (old style).
557 (AtomicAnd8 ptr val mem) => (ANDBlock ptr val mem)
558 (AtomicAnd32 ptr val mem) => (ANDLlock ptr val mem)
559 (AtomicOr8 ptr val mem) => (ORBlock ptr val mem)
560 (AtomicOr32 ptr val mem) => (ORLlock ptr val mem)
561
562 // Atomic memory logical operations (new style).
563 (Atomic(And64|And32|Or64|Or32)value ptr val mem) => (LoweredAtomic(And64|And32|Or64|Or32) ptr val mem)
564
565 // Write barrier.
566 (WB ...) => (LoweredWB ...)
567
568 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
569 (LoweredPanicBoundsRR [kind] x (MOVQconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {ssa.PanicBoundsC{C:c}} mem)
570 (LoweredPanicBoundsRR [kind] (MOVQconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {ssa.PanicBoundsC{C:c}} y mem)
571 (LoweredPanicBoundsRC [kind] {p} (MOVQconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:c, Cy:p.C}} mem)
572 (LoweredPanicBoundsCR [kind] {p} (MOVQconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:p.C, Cy:c}} mem)
573
574 // lowering rotates
575 (RotateLeft8 ...) => (ROLB ...)
576 (RotateLeft16 ...) => (ROLW ...)
577 (RotateLeft32 ...) => (ROLL ...)
578 (RotateLeft64 ...) => (ROLQ ...)
579
580 // ***************************
581 // Above: lowering rules
582 // Below: optimizations
583 // ***************************
584 // TODO: Should the optimizations be a separate pass?
585
586 // Fold boolean tests into blocks
587 (NE (TESTB (SETL cmp) (SETL cmp)) yes no) => (LT cmp yes no)
588 (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no) => (LE cmp yes no)
589 (NE (TESTB (SETG cmp) (SETG cmp)) yes no) => (GT cmp yes no)
590 (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no) => (GE cmp yes no)
591 (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no) => (EQ cmp yes no)
592 (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no) => (NE cmp yes no)
593 (NE (TESTB (SETB cmp) (SETB cmp)) yes no) => (ULT cmp yes no)
594 (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no) => (ULE cmp yes no)
595 (NE (TESTB (SETA cmp) (SETA cmp)) yes no) => (UGT cmp yes no)
596 (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no) => (UGE cmp yes no)
597 (NE (TESTB (SETO cmp) (SETO cmp)) yes no) => (OS cmp yes no)
598
599 // Unsigned comparisons to 0/1
600 (ULT (TEST(Q|L|W|B) x x) yes no) => (First no yes)
601 (UGE (TEST(Q|L|W|B) x x) yes no) => (First yes no)
602 (SETB (TEST(Q|L|W|B) x x)) => (ConstBool [false])
603 (SETAE (TEST(Q|L|W|B) x x)) => (ConstBool [true])
604
605 // x & 1 != 0 -> x & 1
606 (SETNE (TEST(B|W)const [1] x)) => (AND(L|L)const [1] x)
607 (SETB (BT(L|Q)const [0] x)) => (AND(L|Q)const [1] x)
608 // x & 1 == 0 -> (x & 1) ^ 1
609 (SETAE (BT(L|Q)const [0] x)) => (XORLconst [1] (ANDLconst <typ.Bool> [1] x))
610
611 // Shorten compare by rewriting x < 128 as x <= 127, which can be encoded in a single-byte immediate on x86.
612 (SETL c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETLE (CMP(Q|L)const [127] x))
613 (SETB c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETBE (CMP(Q|L)const [127] x))
614
615 // x >= 128 -> x > 127
616 (SETGE c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETG (CMP(Q|L)const [127] x))
617 (SETAE c:(CMP(Q|L)const [128] x)) && c.Uses == 1 => (SETA (CMP(Q|L)const [127] x))
618
619 (CMOVQLT x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVQLE x y (CMP(Q|L)const [127] z))
620 (CMOVLLT x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVLLE x y (CMP(Q|L)const [127] z))
621 (LT c:(CMP(Q|L)const [128] z) yes no) && c.Uses == 1 => (LE (CMP(Q|L)const [127] z) yes no)
622 (CMOVQGE x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVQGT x y (CMP(Q|L)const [127] z))
623 (CMOVLGE x y c:(CMP(Q|L)const [128] z)) && c.Uses == 1 => (CMOVLGT x y (CMP(Q|L)const [127] z))
624 (GE c:(CMP(Q|L)const [128] z) yes no) && c.Uses == 1 => (GT (CMP(Q|L)const [127] z) yes no)
625
626 // Recognize bit tests: a&(1<<b) != 0 for b suitably bounded
627 // Note that BTx instructions use the carry bit, so we need to convert tests for zero flag
628 // into tests for carry flags.
629 // ULT and SETB check the carry flag; they are identical to CS and SETCS. Same, mutatis
630 // mutandis, for UGE and SETAE, and CC and SETCC.
631 ((NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => ((ULT|UGE) (BTL x y))
632 ((NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => ((ULT|UGE) (BTQ x y))
633 ((NE|EQ) (TESTLconst [c] x)) && ssa.IsPowerOfTwo(uint32(c))
634 => ((ULT|UGE) (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
635 ((NE|EQ) (TESTQconst [c] x)) && ssa.IsPowerOfTwo(uint64(c))
636 => ((ULT|UGE) (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
637 ((NE|EQ) (TESTQ (MOVQconst [c]) x)) && ssa.IsPowerOfTwo(uint64(c))
638 => ((ULT|UGE) (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
639 (SET(NE|EQ) (TESTL (SHLL (MOVLconst [1]) x) y)) => (SET(B|AE) (BTL x y))
640 (SET(NE|EQ) (TESTQ (SHLQ (MOVQconst [1]) x) y)) => (SET(B|AE) (BTQ x y))
641 (SET(NE|EQ) (TESTLconst [c] x)) && ssa.IsPowerOfTwo(uint32(c))
642 => (SET(B|AE) (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
643 (SET(NE|EQ) (TESTQconst [c] x)) && ssa.IsPowerOfTwo(uint64(c))
644 => (SET(B|AE) (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
645 (SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && ssa.IsPowerOfTwo(uint64(c))
646 => (SET(B|AE) (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
647 // SET..store variant
648 (SET(NE|EQ)store [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
649 => (SET(B|AE)store [off] {sym} ptr (BTL x y) mem)
650 (SET(NE|EQ)store [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
651 => (SET(B|AE)store [off] {sym} ptr (BTQ x y) mem)
652 (SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && ssa.IsPowerOfTwo(uint32(c))
653 => (SET(B|AE)store [off] {sym} ptr (BTLconst [int8(ssa.Log32u(uint32(c)))] x) mem)
654 (SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && ssa.IsPowerOfTwo(uint64(c))
655 => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(ssa.Log32u(uint32(c)))] x) mem)
656 (SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && ssa.IsPowerOfTwo(uint64(c))
657 => (SET(B|AE)store [off] {sym} ptr (BTQconst [int8(ssa.Log64u(uint64(c)))] x) mem)
658
659 // Handle bit-testing in the form (a>>b)&1 != 0 by building the above rules
660 // and further combining shifts.
661 (BT(Q|L)const [c] (SHRQconst [d] x)) && (c+d)<64 => (BTQconst [c+d] x)
662 (BT(Q|L)const [c] (ADDQ x x)) && c>1 => (BT(Q|L)const [c-1] x)
663 (BT(Q|L)const [c] (SHLQconst [d] x)) && c>d => (BT(Q|L)const [c-d] x)
664 (BT(Q|L)const [0] s:(SHRQ x y)) => (BTQ y x)
665 (BTLconst [c] (SHRLconst [d] x)) && (c+d)<32 => (BTLconst [c+d] x)
666 (BTLconst [c] (ADDL x x)) && c>1 => (BTLconst [c-1] x)
667 (BTLconst [c] (SHLLconst [d] x)) && c>d => (BTLconst [c-d] x)
668 (BTLconst [0] s:(SHR(L|XL) x y)) => (BTL y x)
669
670 // Rewrite a & 1 != 1 into a & 1 == 0.
671 // Among other things, this lets us turn (a>>b)&1 != 1 into a bit test.
672 (SET(NE|EQ) (CMPLconst [1] s:(ANDLconst [1] _))) => (SET(EQ|NE) (CMPLconst [0] s))
673 (SET(NE|EQ)store [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPLconst [0] s) mem)
674 (SET(NE|EQ) (CMPQconst [1] s:(ANDQconst [1] _))) => (SET(EQ|NE) (CMPQconst [0] s))
675 (SET(NE|EQ)store [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) => (SET(EQ|NE)store [off] {sym} ptr (CMPQconst [0] s) mem)
676
677 // Recognize bit setting (a |= 1<<b) and toggling (a ^= 1<<b)
678 (OR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTS(Q|L) x y)
679 (XOR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) => (BTC(Q|L) x y)
680 // Note: only convert OR/XOR to BTS/BTC if the constant wouldn't fit in
681 // the constant field of the OR/XOR instruction. See issue 61694.
682 ((OR|XOR)Q (MOVQconst [c]) x) && ssa.IsPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31 => (BT(S|C)Qconst [int8(ssa.Log64u(uint64(c)))] x)
683
684 // Recognize bit clearing: a &^= 1<<b
685 (AND(Q|L) (NOT(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y)) x) => (BTR(Q|L) x y)
686 (ANDN(Q|L) x (SHL(Q|L) (MOV(Q|L)const [1]) y)) => (BTR(Q|L) x y)
687 // Note: only convert AND to BTR if the constant wouldn't fit in
688 // the constant field of the AND instruction. See issue 61694.
689 (ANDQ (MOVQconst [c]) x) && ssa.IsPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31 => (BTRQconst [int8(ssa.Log64u(uint64(^c)))] x)
690
691 // Special-case bit patterns on first/last bit.
692 // generic.rules changes ANDs of high-part/low-part masks into a couple of shifts,
693 // for instance:
694 // x & 0xFFFF0000 -> (x >> 16) << 16
695 // x & 0x80000000 -> (x >> 31) << 31
696 //
697 // In case the mask is just one bit (like second example above), it conflicts
698 // with the above rules to detect bit-testing / bit-clearing of first/last bit.
699 // We thus special-case them, by detecting the shift patterns.
700
701 // Special case resetting first/last bit
702 (ADD(L|Q) (SHR(L|Q)const [1] x) (SHR(L|Q)const [1] x))
703 => (AND(L|Q)const [-2] x)
704 (SHRLconst [1] (ADDL x x))
705 => (ANDLconst [0x7fffffff] x)
706 (SHRQconst [1] (ADDQ x x))
707 => (BTRQconst [63] x)
708
709 // Special case testing first/last bit (with double-shift generated by generic.rules)
710 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2)) && z1==z2
711 => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
712 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) && z1==z2
713 => ((SETB|SETAE|ULT|UGE) (BTQconst [31] x))
714 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) && z1==z2
715 => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
716 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) && z1==z2
717 => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
718
719 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) && z1==z2
720 => ((SETB|SETAE|ULT|UGE) (BTQconst [0] x))
721 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) && z1==z2
722 => ((SETB|SETAE|ULT|UGE) (BTLconst [0] x))
723 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) && z1==z2
724 => (SET(B|AE)store [off] {sym} ptr (BTQconst [0] x) mem)
725 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) && z1==z2
726 => (SET(B|AE)store [off] {sym} ptr (BTLconst [0] x) mem)
727
728 // Special-case manually testing last bit with "a>>63 != 0" (without "&1")
729 ((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] x) z2)) && z1==z2
730 => ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
731 ((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] x) z2)) && z1==z2
732 => ((SETB|SETAE|ULT|UGE) (BTLconst [31] x))
733 (SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) && z1==z2
734 => (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
735 (SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) && z1==z2
736 => (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
737
738 // Fold combinations of bit ops on same bit. An example is math.Copysign(c,-1)
739 (BTSQconst [c] (BTRQconst [c] x)) => (BTSQconst [c] x)
740 (BTSQconst [c] (BTCQconst [c] x)) => (BTSQconst [c] x)
741 (BTRQconst [c] (BTSQconst [c] x)) => (BTRQconst [c] x)
742 (BTRQconst [c] (BTCQconst [c] x)) => (BTRQconst [c] x)
743
744 // Fold boolean negation into SETcc.
745 (XORLconst [1] (SETNE x)) => (SETEQ x)
746 (XORLconst [1] (SETEQ x)) => (SETNE x)
747 (XORLconst [1] (SETL x)) => (SETGE x)
748 (XORLconst [1] (SETGE x)) => (SETL x)
749 (XORLconst [1] (SETLE x)) => (SETG x)
750 (XORLconst [1] (SETG x)) => (SETLE x)
751 (XORLconst [1] (SETB x)) => (SETAE x)
752 (XORLconst [1] (SETAE x)) => (SETB x)
753 (XORLconst [1] (SETBE x)) => (SETA x)
754 (XORLconst [1] (SETA x)) => (SETBE x)
755
756 // Special case for floating point - LF/LEF not generated
757 (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no) => (UGT cmp yes no)
758 (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no) => (UGE cmp yes no)
759 (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no) => (EQF cmp yes no)
760 (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no) => (NEF cmp yes no)
761
762 // Disabled because it interferes with the pattern match above and makes worse code.
763 // (SETNEF x) => (ORQ (SETNE <typ.Int8> x) (SETNAN <typ.Int8> x))
764 // (SETEQF x) => (ANDQ (SETEQ <typ.Int8> x) (SETORD <typ.Int8> x))
765
766 // fold constants into instructions
767 (ADDQ x (MOVQconst <t> [c])) && ssa.Is32Bit(c) && !t.IsPtr() => (ADDQconst [int32(c)] x)
768 (ADDQ x (MOVLconst [c])) => (ADDQconst [c] x)
769 (ADDL x (MOVLconst [c])) => (ADDLconst [c] x)
770
771 (SUBQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (SUBQconst x [int32(c)])
772 (SUBQ (MOVQconst [c]) x) && ssa.Is32Bit(c) => (NEGQ (SUBQconst <v.Type> x [int32(c)]))
773 (SUBL x (MOVLconst [c])) => (SUBLconst x [c])
774 (SUBL (MOVLconst [c]) x) => (NEGL (SUBLconst <v.Type> x [c]))
775
776 (MULQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (MULQconst [int32(c)] x)
777 (MULL x (MOVLconst [c])) => (MULLconst [c] x)
778
779 (ANDQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (ANDQconst [int32(c)] x)
780 (ANDL x (MOVLconst [c])) => (ANDLconst [c] x)
781
782 (AND(L|Q)const [c] (AND(L|Q)const [d] x)) => (AND(L|Q)const [c & d] x)
783 (XOR(L|Q)const [c] (XOR(L|Q)const [d] x)) => (XOR(L|Q)const [c ^ d] x)
784 (OR(L|Q)const [c] (OR(L|Q)const [d] x)) => (OR(L|Q)const [c | d] x)
785
786 (MULLconst [c] (MULLconst [d] x)) => (MULLconst [c * d] x)
787 (MULQconst [c] (MULQconst [d] x)) && ssa.Is32Bit(int64(c)*int64(d)) => (MULQconst [c * d] x)
788
789 (ORQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (ORQconst [int32(c)] x)
790 (ORQ x (MOVLconst [c])) => (ORQconst [c] x)
791 (ORL x (MOVLconst [c])) => (ORLconst [c] x)
792
793 (XORQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (XORQconst [int32(c)] x)
794 (XORL x (MOVLconst [c])) => (XORLconst [c] x)
795
796 (SHLQ x (MOV(Q|L)const [c])) => (SHLQconst [int8(c&63)] x)
797 (SHLL x (MOV(Q|L)const [c])) => (SHLLconst [int8(c&31)] x)
798
799 (SHRQ x (MOV(Q|L)const [c])) => (SHRQconst [int8(c&63)] x)
800 (SHRL x (MOV(Q|L)const [c])) => (SHRLconst [int8(c&31)] x)
801 (SHRW x (MOV(Q|L)const [c])) && c&31 < 16 => (SHRWconst [int8(c&31)] x)
802 (SHRW _ (MOV(Q|L)const [c])) && c&31 >= 16 => (MOVLconst [0])
803 (SHRB x (MOV(Q|L)const [c])) && c&31 < 8 => (SHRBconst [int8(c&31)] x)
804 (SHRB _ (MOV(Q|L)const [c])) && c&31 >= 8 => (MOVLconst [0])
805
806 (SARQ x (MOV(Q|L)const [c])) => (SARQconst [int8(c&63)] x)
807 (SARL x (MOV(Q|L)const [c])) => (SARLconst [int8(c&31)] x)
808 (SARW x (MOV(Q|L)const [c])) => (SARWconst [int8(min(int64(c)&31,15))] x)
809 (SARB x (MOV(Q|L)const [c])) => (SARBconst [int8(min(int64(c)&31,7))] x)
810
811 // Operations which don't affect the low 6/5 bits of the shift amount are NOPs.
812 ((SHLQ|SHRQ|SARQ) x (ADDQconst [c] y)) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x y)
813 ((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ADDQconst [c] y))) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
814 ((SHLQ|SHRQ|SARQ) x (ANDQconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
815 ((SHLQ|SHRQ|SARQ) x (NEGQ <t> (ANDQconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGQ <t> y))
816
817 ((SHLL|SHRL|SARL) x (ADDQconst [c] y)) && c & 31 == 0 => ((SHLL|SHRL|SARL) x y)
818 ((SHLL|SHRL|SARL) x (NEGQ <t> (ADDQconst [c] y))) && c & 31 == 0 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
819 ((SHLL|SHRL|SARL) x (ANDQconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
820 ((SHLL|SHRL|SARL) x (NEGQ <t> (ANDQconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
821
822 ((SHLQ|SHRQ|SARQ) x (ADDLconst [c] y)) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x y)
823 ((SHLQ|SHRQ|SARQ) x (NEGL <t> (ADDLconst [c] y))) && c & 63 == 0 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
824 ((SHLQ|SHRQ|SARQ) x (ANDLconst [c] y)) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x y)
825 ((SHLQ|SHRQ|SARQ) x (NEGL <t> (ANDLconst [c] y))) && c & 63 == 63 => ((SHLQ|SHRQ|SARQ) x (NEGL <t> y))
826
827 ((SHLL|SHRL|SARL) x (ADDLconst [c] y)) && c & 31 == 0 => ((SHLL|SHRL|SARL) x y)
828 ((SHLL|SHRL|SARL) x (NEGL <t> (ADDLconst [c] y))) && c & 31 == 0 => ((SHLL|SHRL|SARL) x (NEGL <t> y))
829 ((SHLL|SHRL|SARL) x (ANDLconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
830 ((SHLL|SHRL|SARL) x (NEGL <t> (ANDLconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGL <t> y))
831
832 // rotate left negative = rotate right
833 (ROLQ x (NEG(Q|L) y)) => (RORQ x y)
834 (ROLL x (NEG(Q|L) y)) => (RORL x y)
835 (ROLW x (NEG(Q|L) y)) => (RORW x y)
836 (ROLB x (NEG(Q|L) y)) => (RORB x y)
837
838 // rotate right negative = rotate left
839 (RORQ x (NEG(Q|L) y)) => (ROLQ x y)
840 (RORL x (NEG(Q|L) y)) => (ROLL x y)
841 (RORW x (NEG(Q|L) y)) => (ROLW x y)
842 (RORB x (NEG(Q|L) y)) => (ROLB x y)
843
844 // rotate by constants
845 (ROLQ x (MOV(Q|L)const [c])) => (ROLQconst [int8(c&63)] x)
846 (ROLL x (MOV(Q|L)const [c])) => (ROLLconst [int8(c&31)] x)
847 (ROLW x (MOV(Q|L)const [c])) => (ROLWconst [int8(c&15)] x)
848 (ROLB x (MOV(Q|L)const [c])) => (ROLBconst [int8(c&7) ] x)
849
850 (RORQ x (MOV(Q|L)const [c])) => (ROLQconst [int8((-c)&63)] x)
851 (RORL x (MOV(Q|L)const [c])) => (ROLLconst [int8((-c)&31)] x)
852 (RORW x (MOV(Q|L)const [c])) => (ROLWconst [int8((-c)&15)] x)
853 (RORB x (MOV(Q|L)const [c])) => (ROLBconst [int8((-c)&7) ] x)
854
855 // Constant shift simplifications
856 ((SHLQ|SHRQ|SARQ)const x [0]) => x
857 ((SHLL|SHRL|SARL)const x [0]) => x
858 ((SHRW|SARW)const x [0]) => x
859 ((SHRB|SARB)const x [0]) => x
860 ((ROLQ|ROLL|ROLW|ROLB)const x [0]) => x
861
862 // Note: the word and byte shifts keep the low 5 bits (not the low 4 or 3 bits)
863 // because the x86 instructions are defined to use all 5 bits of the shift even
864 // for the small shifts. I don't think we'll ever generate a weird shift (e.g.
865 // (SHRW x (MOVLconst [24])), but just in case.
866
867 (CMPQ x (MOVQconst [c])) && ssa.Is32Bit(c) => (CMPQconst x [int32(c)])
868 (CMPQ (MOVQconst [c]) x) && ssa.Is32Bit(c) => (InvertFlags (CMPQconst x [int32(c)]))
869 (CMPL x (MOVLconst [c])) => (CMPLconst x [c])
870 (CMPL (MOVLconst [c]) x) => (InvertFlags (CMPLconst x [c]))
871 (CMPW x (MOVLconst [c])) => (CMPWconst x [int16(c)])
872 (CMPW (MOVLconst [c]) x) => (InvertFlags (CMPWconst x [int16(c)]))
873 (CMPB x (MOVLconst [c])) => (CMPBconst x [int8(c)])
874 (CMPB (MOVLconst [c]) x) => (InvertFlags (CMPBconst x [int8(c)]))
875
876 // Canonicalize the order of arguments to comparisons - helps with CSE.
877 (CMP(Q|L|W|B) x y) && ssa.CanonLessThan(x,y) => (InvertFlags (CMP(Q|L|W|B) y x))
878
879 // Using MOVZX instead of AND is cheaper.
880 (AND(Q|L)const [ 0xFF] x) => (MOVBQZX x)
881 (AND(Q|L)const [0xFFFF] x) => (MOVWQZX x)
882 // This rule is currently invalid because 0xFFFFFFFF is not representable by a signed int32.
883 // Commenting out for now, because it also can't trigger because of the is32bit guard on the
884 // ANDQconst lowering-rule, above, prevents 0xFFFFFFFF from matching (for the same reason)
885 // Using an alternate form of this rule segfaults some binaries because of
886 // adverse interactions with other passes.
887 // (ANDQconst [0xFFFFFFFF] x) => (MOVLQZX x)
888
889 // strength reduction
890 (MUL(Q|L)const [ 0] _) => (MOV(Q|L)const [0])
891 (MUL(Q|L)const [ 1] x) => x
892 (MULQconst [c] x) && ssa.CanMulStrengthReduce(config, int64(c)) => {ssa.MulStrengthReduce(v, x, int64(c))}
893 (MULLconst [c] x) && v.Type.Size() <= 4 && ssa.CanMulStrengthReduce32(config, c) => {ssa.MulStrengthReduce32(v, x, c)}
894
895 // Prefer addition when shifting left by one
896 (SHL(Q|L)const [1] x) => (ADD(Q|L) x x)
897
898 // combine add/shift into LEAQ/LEAL
899 (ADD(L|Q) x (SHL(L|Q)const [3] y)) => (LEA(L|Q)8 x y)
900 (ADD(L|Q) x (SHL(L|Q)const [2] y)) => (LEA(L|Q)4 x y)
901 (ADD(L|Q) x (ADD(L|Q) y y)) => (LEA(L|Q)2 x y)
902 (ADD(L|Q) x (ADD(L|Q) x y)) => (LEA(L|Q)2 y x)
903
904 // combine ADDQ/ADDQconst into LEAQ1/LEAL1
905 (ADD(Q|L)const [c] (ADD(Q|L) x y)) => (LEA(Q|L)1 [c] x y)
906 (ADD(Q|L) (ADD(Q|L)const [c] x) y) => (LEA(Q|L)1 [c] x y)
907 (ADD(Q|L)const [c] (ADD(Q|L) x x)) => (LEA(Q|L)1 [c] x x)
908
909 // fold ADDQ/ADDL into LEAQ/LEAL
910 (ADD(Q|L)const [c] (LEA(Q|L) [d] {s} x)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
911 (LEA(Q|L) [c] {s} (ADD(Q|L)const [d] x)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L) [c+d] {s} x)
912 (LEA(Q|L) [c] {s} (ADD(Q|L) x y)) && x.Op != ssaop.OpSB && y.Op != ssaop.OpSB => (LEA(Q|L)1 [c] {s} x y)
913 (ADD(Q|L) x (LEA(Q|L) [c] {s} y)) && x.Op != ssaop.OpSB && y.Op != ssaop.OpSB => (LEA(Q|L)1 [c] {s} x y)
914
915 // fold ADDQconst/ADDLconst into LEAQx/LEALx
916 (ADD(Q|L)const [c] (LEA(Q|L)1 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)1 [c+d] {s} x y)
917 (ADD(Q|L)const [c] (LEA(Q|L)2 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)2 [c+d] {s} x y)
918 (ADD(Q|L)const [c] (LEA(Q|L)4 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)4 [c+d] {s} x y)
919 (ADD(Q|L)const [c] (LEA(Q|L)8 [d] {s} x y)) && ssa.Is32Bit(int64(c)+int64(d)) => (LEA(Q|L)8 [c+d] {s} x y)
920 (LEA(Q|L)1 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB => (LEA(Q|L)1 [c+d] {s} x y)
921 (LEA(Q|L)2 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB => (LEA(Q|L)2 [c+d] {s} x y)
922 (LEA(Q|L)2 [c] {s} x (ADD(Q|L)const [d] y)) && ssa.Is32Bit(int64(c)+2*int64(d)) && y.Op != ssaop.OpSB => (LEA(Q|L)2 [c+2*d] {s} x y)
923 (LEA(Q|L)4 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB => (LEA(Q|L)4 [c+d] {s} x y)
924 (LEA(Q|L)4 [c] {s} x (ADD(Q|L)const [d] y)) && ssa.Is32Bit(int64(c)+4*int64(d)) && y.Op != ssaop.OpSB => (LEA(Q|L)4 [c+4*d] {s} x y)
925 (LEA(Q|L)8 [c] {s} (ADD(Q|L)const [d] x) y) && ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB => (LEA(Q|L)8 [c+d] {s} x y)
926 (LEA(Q|L)8 [c] {s} x (ADD(Q|L)const [d] y)) && ssa.Is32Bit(int64(c)+8*int64(d)) && y.Op != ssaop.OpSB => (LEA(Q|L)8 [c+8*d] {s} x y)
927
928 // fold shifts into LEAQx/LEALx
929 (LEA(Q|L)1 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)2 [c] {s} x y)
930 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)4 [c] {s} x y)
931 (LEA(Q|L)1 [c] {s} x (SHL(Q|L)const [3] y)) => (LEA(Q|L)8 [c] {s} x y)
932 (LEA(Q|L)2 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)4 [c] {s} x y)
933 (LEA(Q|L)2 [c] {s} x (SHL(Q|L)const [2] y)) => (LEA(Q|L)8 [c] {s} x y)
934 (LEA(Q|L)4 [c] {s} x z:(ADD(Q|L) y y)) && x != z => (LEA(Q|L)8 [c] {s} x y)
935
936 // (x + x) << 1 -> x << 2
937 (LEA(Q|L)2 [0] {s} (ADD(Q|L) x x) x) && s == nil => (SHL(Q|L)const [2] x)
938
939 // (x + x) << 2 -> x << 3 and similar
940 (SHLQconst [c] (ADDQ x x)) && c < 63 => (SHLQconst [c+1] x)
941 (SHLLconst [c] (ADDL x x)) && c < 31 => (SHLLconst [c+1] x)
942
943 // reverse ordering of compare instruction
944 (SETL (InvertFlags x)) => (SETG x)
945 (SETG (InvertFlags x)) => (SETL x)
946 (SETB (InvertFlags x)) => (SETA x)
947 (SETA (InvertFlags x)) => (SETB x)
948 (SETLE (InvertFlags x)) => (SETGE x)
949 (SETGE (InvertFlags x)) => (SETLE x)
950 (SETBE (InvertFlags x)) => (SETAE x)
951 (SETAE (InvertFlags x)) => (SETBE x)
952 (SETEQ (InvertFlags x)) => (SETEQ x)
953 (SETNE (InvertFlags x)) => (SETNE x)
954
955 (SETLstore [off] {sym} ptr (InvertFlags x) mem) => (SETGstore [off] {sym} ptr x mem)
956 (SETGstore [off] {sym} ptr (InvertFlags x) mem) => (SETLstore [off] {sym} ptr x mem)
957 (SETBstore [off] {sym} ptr (InvertFlags x) mem) => (SETAstore [off] {sym} ptr x mem)
958 (SETAstore [off] {sym} ptr (InvertFlags x) mem) => (SETBstore [off] {sym} ptr x mem)
959 (SETLEstore [off] {sym} ptr (InvertFlags x) mem) => (SETGEstore [off] {sym} ptr x mem)
960 (SETGEstore [off] {sym} ptr (InvertFlags x) mem) => (SETLEstore [off] {sym} ptr x mem)
961 (SETBEstore [off] {sym} ptr (InvertFlags x) mem) => (SETAEstore [off] {sym} ptr x mem)
962 (SETAEstore [off] {sym} ptr (InvertFlags x) mem) => (SETBEstore [off] {sym} ptr x mem)
963 (SETEQstore [off] {sym} ptr (InvertFlags x) mem) => (SETEQstore [off] {sym} ptr x mem)
964 (SETNEstore [off] {sym} ptr (InvertFlags x) mem) => (SETNEstore [off] {sym} ptr x mem)
965
966 // sign extended loads
967 // Note: The combined instruction must end up in the same block
968 // as the original load. If not, we end up making a value with
969 // memory type live in two different blocks, which can lead to
970 // multiple memory values alive simultaneously.
971 // Make sure we don't combine these ops if the load has another use.
972 // This prevents a single load from being split into multiple loads
973 // which then might return different values. See test/atomicload.go.
974 (MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
975 (MOVBQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
976 (MOVBQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
977 (MOVBQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
978 (MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
979 (MOVBQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
980 (MOVBQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
981 (MOVBQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
982 (MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
983 (MOVWQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
984 (MOVWQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
985 (MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
986 (MOVWQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
987 (MOVWQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
988 (MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
989 (MOVLQSX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
990 (MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
991 (MOVLQZX x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
992
993 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
994 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVBQZX x)
995 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVWQZX x)
996 (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVLQZX x)
997 (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => x
998 (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVBQSX x)
999 (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVWQSX x)
1000 (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) => (MOVLQSX x)
1001
1002 // Fold extensions and ANDs together.
1003 (MOVBQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x)
1004 (MOVWQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x)
1005 (MOVLQZX (ANDLconst [c] x)) => (ANDLconst [c] x)
1006 (MOVBQSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x)
1007 (MOVWQSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x)
1008 (MOVLQSX (ANDLconst [c] x)) && uint32(c) & 0x80000000 == 0 => (ANDLconst [c & 0x7fffffff] x)
1009
1010 // Don't extend before storing
1011 (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) => (MOVLstore [off] {sym} ptr x mem)
1012 (MOVWstore [off] {sym} ptr (MOVWQSX x) mem) => (MOVWstore [off] {sym} ptr x mem)
1013 (MOVBstore [off] {sym} ptr (MOVBQSX x) mem) => (MOVBstore [off] {sym} ptr x mem)
1014 (MOVLstore [off] {sym} ptr (MOVLQZX x) mem) => (MOVLstore [off] {sym} ptr x mem)
1015 (MOVWstore [off] {sym} ptr (MOVWQZX x) mem) => (MOVWstore [off] {sym} ptr x mem)
1016 (MOVBstore [off] {sym} ptr (MOVBQZX x) mem) => (MOVBstore [off] {sym} ptr x mem)
1017
1018 // fold constants into memory operations
1019 // Note that this is not always a good idea because if not all the uses of
1020 // the ADDQconst get eliminated, we still have to compute the ADDQconst and we now
1021 // have potentially two live values (ptr and (ADDQconst [off] ptr)) instead of one.
1022 // Nevertheless, let's do it!
1023 (MOV(Q|L|W|B|SS|SD|O)load [off1] {sym} (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1024 (MOV(Q|L|W|B|SS|SD|O)load [off1+off2] {sym} ptr mem)
1025 (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym} (ADDQconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1026 (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {sym} ptr val mem)
1027 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1028 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {sym} base val mem)
1029 ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1030 ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {sym} val base mem)
1031 ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1032 ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
1033 (CMP(Q|L|W|B)load [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1034 (CMP(Q|L|W|B)load [off1+off2] {sym} base val mem)
1035 (CMP(Q|L|W|B)constload [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
1036 (CMP(Q|L|W|B)constload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
1037
1038 ((ADD|SUB|MUL|DIV)SSload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1039 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {sym} val base mem)
1040 ((ADD|SUB|MUL|DIV)SDload [off1] {sym} val (ADDQconst [off2] base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1041 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {sym} val base mem)
1042 ((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
1043 ((ADD|AND|OR|XOR)Qconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
1044 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
1045 ((ADD|AND|OR|XOR)Lconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
1046 ((ADD|AND|OR|XOR)Wconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
1047 ((ADD|AND|OR|XOR)Wconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
1048 ((ADD|AND|OR|XOR)Bconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ssa.ValAndOff(valoff1).CanAdd32(off2) =>
1049 ((ADD|AND|OR|XOR)Bconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
1050 ((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1051 ((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {sym} base val mem)
1052 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDQconst [off2] base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1053 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)
1054
1055 // Fold constants into stores.
1056 (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validVal(c) =>
1057 (MOVQstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
1058 (MOVLstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1059 (MOVLstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
1060 (MOVWstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1061 (MOVWstoreconst [ssa.MakeValAndOff(int32(int16(c)),off)] {sym} ptr mem)
1062 (MOVBstore [off] {sym} ptr (MOV(L|Q)const [c]) mem) =>
1063 (MOVBstoreconst [ssa.MakeValAndOff(int32(int8(c)),off)] {sym} ptr mem)
1064
1065 // Fold address offsets into constant stores.
1066 (MOV(Q|L|W|B|O)storeconst [sc] {s} (ADDQconst [off] ptr) mem) && ssa.ValAndOff(sc).CanAdd32(off) =>
1067 (MOV(Q|L|W|B|O)storeconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)
1068
1069 // We need to fold LEAQ into the MOVx ops so that the live variable analysis knows
1070 // what variables are being read/written by the ops.
1071 (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
1072 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1073 (MOV(Q|L|W|B|SS|SD|O|BQSX|WQSX|LQSX)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
1074 (MOV(Q|L|W|B|SS|SD|O)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1075 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1076 (MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
1077 (MOV(Q|L|W|B|O)storeconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off) =>
1078 (MOV(Q|L|W|B|O)storeconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
1079 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1080 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1081 (SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
1082 ((ADD|SUB|AND|OR|XOR)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1083 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1084 ((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
1085 ((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1086 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1087 ((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
1088 (CMP(Q|L|W|B)load [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1089 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1090 (CMP(Q|L|W|B)load [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
1091 (CMP(Q|L|W|B)constload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1092 && ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
1093 (CMP(Q|L|W|B)constload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
1094
1095 ((ADD|SUB|MUL|DIV)SSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1096 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1097 ((ADD|SUB|MUL|DIV)SSload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
1098 ((ADD|SUB|MUL|DIV)SDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
1099 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1100 ((ADD|SUB|MUL|DIV)SDload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
1101 ((ADD|AND|OR|XOR)Qconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1102 && ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
1103 ((ADD|AND|OR|XOR)Qconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
1104 ((ADD|AND|OR|XOR)Lconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1105 && ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
1106 ((ADD|AND|OR|XOR)Lconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
1107 ((ADD|AND|OR|XOR)Wconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1108 && ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
1109 ((ADD|AND|OR|XOR)Wconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
1110 ((ADD|AND|OR|XOR)Bconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
1111 && ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2) =>
1112 ((ADD|AND|OR|XOR)Bconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
1113 ((ADD|SUB|AND|OR|XOR)Qmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1114 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1115 ((ADD|SUB|AND|OR|XOR)Qmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
1116 ((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
1117 && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1118 ((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
1119
1120 // fold LEAQs together
1121 (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1122 (LEAQ [off1+off2] {ssa.MergeSym(sym1,sym2)} x)
1123
1124 // LEAQ into LEAQ1
1125 (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
1126 (LEAQ1 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1127
1128 // LEAQ1 into LEAQ
1129 (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1130 (LEAQ1 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1131
1132 // LEAQ into LEAQ[248]
1133 (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
1134 (LEAQ2 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1135 (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
1136 (LEAQ4 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1137 (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB =>
1138 (LEAQ8 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1139
1140 // LEAQ[248] into LEAQ
1141 (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1142 (LEAQ2 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1143 (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1144 (LEAQ4 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1145 (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1146 (LEAQ8 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
1147
1148 // LEAQ[1248] into LEAQ[1248]. Only some such merges are possible.
1149 (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1150 (LEAQ2 [off1+off2] {ssa.MergeSym(sym1, sym2)} x y)
1151 (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y)) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1152 (LEAQ2 [off1+off2] {ssa.MergeSym(sym1, sym2)} y x)
1153 (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && ssa.Is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil =>
1154 (LEAQ4 [off1+2*off2] {sym1} x y)
1155 (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y)) && ssa.Is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil =>
1156 (LEAQ8 [off1+4*off2] {sym1} x y)
1157 // TODO: more?
1158
1159 // Lower LEAQ2/4/8 when the offset is a constant
1160 (LEAQ2 [off] {sym} x (MOV(Q|L)const [scale])) && ssa.Is32Bit(int64(off)+int64(scale)*2) =>
1161 (LEAQ [off+int32(scale)*2] {sym} x)
1162 (LEAQ4 [off] {sym} x (MOV(Q|L)const [scale])) && ssa.Is32Bit(int64(off)+int64(scale)*4) =>
1163 (LEAQ [off+int32(scale)*4] {sym} x)
1164 (LEAQ8 [off] {sym} x (MOV(Q|L)const [scale])) && ssa.Is32Bit(int64(off)+int64(scale)*8) =>
1165 (LEAQ [off+int32(scale)*8] {sym} x)
1166
1167 // Absorb InvertFlags into branches.
1168 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
1169 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
1170 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
1171 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
1172 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
1173 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
1174 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
1175 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
1176 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
1177 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
1178
1179 // Constant comparisons.
1180 (CMPQconst (MOVQconst [x]) [y]) && x==int64(y) => (FlagEQ)
1181 (CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)<uint64(int64(y)) => (FlagLT_ULT)
1182 (CMPQconst (MOVQconst [x]) [y]) && x<int64(y) && uint64(x)>uint64(int64(y)) => (FlagLT_UGT)
1183 (CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)<uint64(int64(y)) => (FlagGT_ULT)
1184 (CMPQconst (MOVQconst [x]) [y]) && x>int64(y) && uint64(x)>uint64(int64(y)) => (FlagGT_UGT)
1185 (CMPLconst (MOVLconst [x]) [y]) && x==y => (FlagEQ)
1186 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)<uint32(y) => (FlagLT_ULT)
1187 (CMPLconst (MOVLconst [x]) [y]) && x<y && uint32(x)>uint32(y) => (FlagLT_UGT)
1188 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)<uint32(y) => (FlagGT_ULT)
1189 (CMPLconst (MOVLconst [x]) [y]) && x>y && uint32(x)>uint32(y) => (FlagGT_UGT)
1190 (CMPWconst (MOVLconst [x]) [y]) && int16(x)==y => (FlagEQ)
1191 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)<uint16(y) => (FlagLT_ULT)
1192 (CMPWconst (MOVLconst [x]) [y]) && int16(x)<y && uint16(x)>uint16(y) => (FlagLT_UGT)
1193 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)<uint16(y) => (FlagGT_ULT)
1194 (CMPWconst (MOVLconst [x]) [y]) && int16(x)>y && uint16(x)>uint16(y) => (FlagGT_UGT)
1195 (CMPBconst (MOVLconst [x]) [y]) && int8(x)==y => (FlagEQ)
1196 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)<uint8(y) => (FlagLT_ULT)
1197 (CMPBconst (MOVLconst [x]) [y]) && int8(x)<y && uint8(x)>uint8(y) => (FlagLT_UGT)
1198 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)<uint8(y) => (FlagGT_ULT)
1199 (CMPBconst (MOVLconst [x]) [y]) && int8(x)>y && uint8(x)>uint8(y) => (FlagGT_UGT)
1200
1201 // CMPQconst requires a 32 bit const, but we can still constant-fold 64 bit consts.
1202 // In theory this applies to any of the simplifications above,
1203 // but CMPQ is the only one I've actually seen occur.
1204 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x==y => (FlagEQ)
1205 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)<uint64(y) => (FlagLT_ULT)
1206 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x<y && uint64(x)>uint64(y) => (FlagLT_UGT)
1207 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)<uint64(y) => (FlagGT_ULT)
1208 (CMPQ (MOVQconst [x]) (MOVQconst [y])) && x>y && uint64(x)>uint64(y) => (FlagGT_UGT)
1209
1210 // Other known comparisons.
1211 (CMPQconst (MOVBQZX _) [c]) && 0xFF < c => (FlagLT_ULT)
1212 (CMPQconst (MOVWQZX _) [c]) && 0xFFFF < c => (FlagLT_ULT)
1213 (CMPLconst (SHRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n) => (FlagLT_ULT)
1214 (CMPQconst (SHRQconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n) => (FlagLT_ULT)
1215 (CMPQconst (ANDQconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1216 (CMPQconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1217 (CMPLconst (ANDLconst _ [m]) [n]) && 0 <= m && m < n => (FlagLT_ULT)
1218 (CMPWconst (ANDLconst _ [m]) [n]) && 0 <= int16(m) && int16(m) < n => (FlagLT_ULT)
1219 (CMPBconst (ANDLconst _ [m]) [n]) && 0 <= int8(m) && int8(m) < n => (FlagLT_ULT)
1220
1221 // TESTQ c c sets flags like CMPQ c 0.
1222 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c == 0 => (FlagEQ)
1223 (TESTLconst [c] (MOVLconst [c])) && c == 0 => (FlagEQ)
1224 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c < 0 => (FlagLT_UGT)
1225 (TESTLconst [c] (MOVLconst [c])) && c < 0 => (FlagLT_UGT)
1226 (TESTQconst [c] (MOVQconst [d])) && int64(c) == d && c > 0 => (FlagGT_UGT)
1227 (TESTLconst [c] (MOVLconst [c])) && c > 0 => (FlagGT_UGT)
1228
1229 // TODO: DIVxU also.
1230
1231 // Absorb flag constants into SBB ops.
1232 (SBBQcarrymask (FlagEQ)) => (MOVQconst [0])
1233 (SBBQcarrymask (FlagLT_ULT)) => (MOVQconst [-1])
1234 (SBBQcarrymask (FlagLT_UGT)) => (MOVQconst [0])
1235 (SBBQcarrymask (FlagGT_ULT)) => (MOVQconst [-1])
1236 (SBBQcarrymask (FlagGT_UGT)) => (MOVQconst [0])
1237 (SBBLcarrymask (FlagEQ)) => (MOVLconst [0])
1238 (SBBLcarrymask (FlagLT_ULT)) => (MOVLconst [-1])
1239 (SBBLcarrymask (FlagLT_UGT)) => (MOVLconst [0])
1240 (SBBLcarrymask (FlagGT_ULT)) => (MOVLconst [-1])
1241 (SBBLcarrymask (FlagGT_UGT)) => (MOVLconst [0])
1242
1243 // Absorb flag constants into branches.
1244 ((EQ|LE|GE|ULE|UGE) (FlagEQ) yes no) => (First yes no)
1245 ((NE|LT|GT|ULT|UGT) (FlagEQ) yes no) => (First no yes)
1246 ((NE|LT|LE|ULT|ULE) (FlagLT_ULT) yes no) => (First yes no)
1247 ((EQ|GT|GE|UGT|UGE) (FlagLT_ULT) yes no) => (First no yes)
1248 ((NE|LT|LE|UGT|UGE) (FlagLT_UGT) yes no) => (First yes no)
1249 ((EQ|GT|GE|ULT|ULE) (FlagLT_UGT) yes no) => (First no yes)
1250 ((NE|GT|GE|ULT|ULE) (FlagGT_ULT) yes no) => (First yes no)
1251 ((EQ|LT|LE|UGT|UGE) (FlagGT_ULT) yes no) => (First no yes)
1252 ((NE|GT|GE|UGT|UGE) (FlagGT_UGT) yes no) => (First yes no)
1253 ((EQ|LT|LE|ULT|ULE) (FlagGT_UGT) yes no) => (First no yes)
1254
1255 // Absorb flag constants into SETxx ops.
1256 ((SETEQ|SETLE|SETGE|SETBE|SETAE) (FlagEQ)) => (MOVLconst [1])
1257 ((SETNE|SETL|SETG|SETB|SETA) (FlagEQ)) => (MOVLconst [0])
1258 ((SETNE|SETL|SETLE|SETB|SETBE) (FlagLT_ULT)) => (MOVLconst [1])
1259 ((SETEQ|SETG|SETGE|SETA|SETAE) (FlagLT_ULT)) => (MOVLconst [0])
1260 ((SETNE|SETL|SETLE|SETA|SETAE) (FlagLT_UGT)) => (MOVLconst [1])
1261 ((SETEQ|SETG|SETGE|SETB|SETBE) (FlagLT_UGT)) => (MOVLconst [0])
1262 ((SETNE|SETG|SETGE|SETB|SETBE) (FlagGT_ULT)) => (MOVLconst [1])
1263 ((SETEQ|SETL|SETLE|SETA|SETAE) (FlagGT_ULT)) => (MOVLconst [0])
1264 ((SETNE|SETG|SETGE|SETA|SETAE) (FlagGT_UGT)) => (MOVLconst [1])
1265 ((SETEQ|SETL|SETLE|SETB|SETBE) (FlagGT_UGT)) => (MOVLconst [0])
1266
1267 (SETEQstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1268 (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1269 (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1270 (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1271 (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1272
1273 (SETNEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1274 (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1275 (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1276 (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1277 (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1278
1279 (SETLstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1280 (SETLstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1281 (SETLstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1282 (SETLstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1283 (SETLstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1284
1285 (SETLEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1286 (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1287 (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1288 (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1289 (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1290
1291 (SETGstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1292 (SETGstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1293 (SETGstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1294 (SETGstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1295 (SETGstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1296
1297 (SETGEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1298 (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1299 (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1300 (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1301 (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1302
1303 (SETBstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1304 (SETBstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1305 (SETBstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1306 (SETBstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1307 (SETBstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1308
1309 (SETBEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1310 (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1311 (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1312 (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1313 (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1314
1315 (SETAstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1316 (SETAstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1317 (SETAstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1318 (SETAstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1319 (SETAstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1320
1321 (SETAEstore [off] {sym} ptr (FlagEQ) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1322 (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1323 (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1324 (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
1325 (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem) => (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
1326
1327 // Remove redundant *const ops
1328 (ADD(Q|L)const [0] x) => x
1329 (SUB(Q|L)const [0] x) => x
1330 (AND(Q|L)const [0] _) => (MOVLconst [0])
1331 (AND(Q|L)const [-1] x) => x
1332 (OR(Q|L)const [0] x) => x
1333 (OR(Q|L)const [-1] _) => (MOV(Q|L)const [-1])
1334 (XOR(Q|L)const [0] x) => x
1335 // TODO: since we got rid of the W/B versions, we might miss
1336 // things like (ANDLconst [0x100] x) which were formerly
1337 // (ANDBconst [0] x). Probably doesn't happen very often.
1338 // If we cared, we might do:
1339 // (ANDLconst <t> [c] x) && t.Size()==1 && int8(x)==0 -> (MOVLconst [0])
1340
1341 // Remove redundant ops
1342 // Not in generic rules, because they may appear after lowering e. g. Slicemask
1343 (NEG(Q|L) (NEG(Q|L) x)) => x
1344 (NEG(Q|L) s:(SUB(Q|L) x y)) && s.Uses == 1 => (SUB(Q|L) y x)
1345
1346 // Convert constant subtracts to constant adds
1347 (SUBQconst [c] x) && c != -(1<<31) => (ADDQconst [-c] x)
1348 (SUBLconst [c] x) => (ADDLconst [-c] x)
1349
1350 // generic constant folding
1351 // TODO: more of this
1352 (ADDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)+d])
1353 (ADDLconst [c] (MOVLconst [d])) => (MOVLconst [c+d])
1354 (ADDQconst [c] (ADDQconst [d] x)) && ssa.Is32Bit(int64(c)+int64(d)) => (ADDQconst [c+d] x)
1355 (ADDLconst [c] (ADDLconst [d] x)) => (ADDLconst [c+d] x)
1356 (SUBQconst (MOVQconst [d]) [c]) => (MOVQconst [d-int64(c)])
1357 (SUBQconst (SUBQconst x [d]) [c]) && ssa.Is32Bit(int64(-c)-int64(d)) => (ADDQconst [-c-d] x)
1358 (SARQconst [c] (MOVQconst [d])) => (MOVQconst [d>>uint64(c)])
1359 (SARLconst [c] (MOVQconst [d])) => (MOVQconst [int64(int32(d))>>uint64(c)])
1360 (SARWconst [c] (MOVQconst [d])) => (MOVQconst [int64(int16(d))>>uint64(c)])
1361 (SARBconst [c] (MOVQconst [d])) => (MOVQconst [int64(int8(d))>>uint64(c)])
1362 (NEG(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [-c])
1363 (MULQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)*d])
1364 (MULLconst [c] (MOVLconst [d])) => (MOVLconst [c*d])
1365 (ANDQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)&d])
1366 (ANDLconst [c] (MOVLconst [d])) => (MOVLconst [c&d])
1367 (ORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)|d])
1368 (ORLconst [c] (MOVLconst [d])) => (MOVLconst [c|d])
1369 (XORQconst [c] (MOVQconst [d])) => (MOVQconst [int64(c)^d])
1370 (XORLconst [c] (MOVLconst [d])) => (MOVLconst [c^d])
1371 (NOT(Q|L) (MOV(Q|L)const [c])) => (MOV(Q|L)const [^c])
1372 (BTSQconst [c] (MOVQconst [d])) => (MOVQconst [d|(1<<uint32(c))])
1373 (BTRQconst [c] (MOVQconst [d])) => (MOVQconst [d&^(1<<uint32(c))])
1374 (BTCQconst [c] (MOVQconst [d])) => (MOVQconst [d^(1<<uint32(c))])
1375
1376 // If c or d doesn't fit into 32 bits, then we can't construct ORQconst,
1377 // but we can still constant-fold.
1378 // In theory this applies to any of the simplifications above,
1379 // but ORQ is the only one I've actually seen occur.
1380 (ORQ (MOVQconst [c]) (MOVQconst [d])) => (MOVQconst [c|d])
1381
1382 // generic simplifications
1383 // TODO: more of this
1384 (ADD(Q|L) x (NEG(Q|L) y)) => (SUB(Q|L) x y)
1385 (SUB(Q|L) x x) => (MOVLconst [0])
1386 (AND(Q|L) x x) => x
1387 (OR(Q|L) x x) => x
1388 (XOR(Q|L) x x) => (MOVLconst [0])
1389
1390 (SHLLconst [d] (MOVLconst [c])) => (MOVLconst [c << uint64(d)])
1391 (SHLQconst [d] (MOVQconst [c])) => (MOVQconst [c << uint64(d)])
1392 (SHLQconst [d] (MOVLconst [c])) => (MOVQconst [int64(c) << uint64(d)])
1393
1394 // Fold NEG into ADDconst/MULconst. Take care to keep c in 32 bit range.
1395 (NEGQ (ADDQconst [c] (NEGQ x))) && c != -(1<<31) => (ADDQconst [-c] x)
1396 (MULQconst [c] (NEGQ x)) && c != -(1<<31) => (MULQconst [-c] x)
1397
1398 // checking AND against 0.
1399 (CMP(Q|L|W|B)const a:(AND(Q|L|L|L) x y) [0]) && a.Uses == 1 => (TEST(Q|L|W|B) x y)
1400 (CMPQconst a:(ANDQconst [c] x) [0]) && a.Uses == 1 => (TESTQconst [c] x)
1401 (CMPLconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTLconst [c] x)
1402 (CMPWconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTWconst [int16(c)] x)
1403 (CMPBconst a:(ANDLconst [c] x) [0]) && a.Uses == 1 => (TESTBconst [int8(c)] x)
1404
1405 // Convert TESTx to TESTxconst if possible.
1406 (TESTQ (MOVQconst [c]) x) && ssa.Is32Bit(c) => (TESTQconst [int32(c)] x)
1407 (TESTL (MOVLconst [c]) x) => (TESTLconst [c] x)
1408 (TESTW (MOVLconst [c]) x) => (TESTWconst [int16(c)] x)
1409 (TESTB (MOVLconst [c]) x) => (TESTBconst [int8(c)] x)
1410
1411 // TEST %reg,%reg is shorter than CMP
1412 (CMP(Q|L|W|B)const x [0]) => (TEST(Q|L|W|B) x x)
1413 (TESTQconst [-1] x) && x.Op != ssaop.OpAMD64MOVQconst => (TESTQ x x)
1414 (TESTLconst [-1] x) && x.Op != ssaop.OpAMD64MOVLconst => (TESTL x x)
1415 (TESTWconst [-1] x) && x.Op != ssaop.OpAMD64MOVLconst => (TESTW x x)
1416 (TESTBconst [-1] x) && x.Op != ssaop.OpAMD64MOVLconst => (TESTB x x)
1417
1418 // Convert LEAQ1 back to ADDQ if we can
1419 (LEAQ1 [0] x y) && v.Aux == nil => (ADDQ x y)
1420
1421 (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem))
1422 && x.Uses == 1
1423 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
1424 && a.Val() == 0
1425 && c.Val() == 0
1426 && ssa.SetPos(v, x.Pos)
1427 && ssa.Clobber(x)
1428 => (MOVOstoreconst [ssa.MakeValAndOff(0,a.Off())] {s} p0 mem)
1429 (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem))
1430 && x.Uses == 1
1431 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off()))
1432 && a.Val() == 0
1433 && c.Val() == 0
1434 && ssa.SetPos(v, x.Pos)
1435 && ssa.Clobber(x)
1436 => (MOVOstoreconst [ssa.MakeValAndOff(0,a.Off())] {s} p0 mem)
1437
1438 // Merge load and op
1439 // TODO: add indexed variants?
1440 ((ADD|SUB|AND|OR|XOR)Q x l:(MOVQload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|AND|OR|XOR)Qload x [off] {sym} ptr mem)
1441 ((ADD|SUB|AND|OR|XOR)L x l:(MOVLload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|AND|OR|XOR)Lload x [off] {sym} ptr mem)
1442 ((ADD|SUB|MUL|DIV)SD x l:(MOVSDload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|MUL|DIV)SDload x [off] {sym} ptr mem)
1443 ((ADD|SUB|MUL|DIV)SS x l:(MOVSSload [off] {sym} ptr mem)) && ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l) => ((ADD|SUB|MUL|DIV)SSload x [off] {sym} ptr mem)
1444 (MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && ssa.Clobber(y) => ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
1445 (MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l) =>
1446 ((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
1447 (MOVQstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Qload x [off] {sym} ptr mem) mem) && y.Uses==1 && ssa.Clobber(y) => ((ADD|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
1448 (MOVQstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)Q l:(MOVQload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l) =>
1449 ((ADD|SUB|AND|OR|XOR)Qmodify [off] {sym} ptr x mem)
1450 (MOVQstore {sym} [off] ptr x:(BT(S|R|C)Qconst [c] l:(MOVQload {sym} [off] ptr mem)) mem) && x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l) =>
1451 (BT(S|R|C)Qconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1452
1453 // Merge ADDQconst and LEAQ into atomic loads.
1454 (MOV(Q|L|B)atomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1455 (MOV(Q|L|B)atomicload [off1+off2] {sym} ptr mem)
1456 (MOV(Q|L|B)atomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) =>
1457 (MOV(Q|L|B)atomicload [off1+off2] {ssa.MergeSym(sym1, sym2)} ptr mem)
1458
1459 // Merge ADDQconst and LEAQ into atomic stores.
1460 (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1461 (XCHGQ [off1+off2] {sym} val ptr mem)
1462 (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB =>
1463 (XCHGQ [off1+off2] {ssa.MergeSym(sym1,sym2)} val ptr mem)
1464 (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1465 (XCHGL [off1+off2] {sym} val ptr mem)
1466 (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB =>
1467 (XCHGL [off1+off2] {ssa.MergeSym(sym1,sym2)} val ptr mem)
1468
1469 // Merge ADDQconst into atomic adds.
1470 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
1471 (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1472 (XADDQlock [off1+off2] {sym} val ptr mem)
1473 (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1474 (XADDLlock [off1+off2] {sym} val ptr mem)
1475
1476 // Merge ADDQconst into atomic compare and swaps.
1477 // TODO: merging LEAQ doesn't work, assembler doesn't like the resulting instructions.
1478 (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1479 (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
1480 (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem) && ssa.Is32Bit(int64(off1)+int64(off2)) =>
1481 (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)
1482
1483 // We don't need the conditional move if we know the arg of BSF is not zero.
1484 (CMOVQEQ x _ (Select1 (BS(F|R)Q (ORQconst [c] _)))) && c != 0 => x
1485 // Extension is unnecessary for trailing zeros.
1486 (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x))) => (BSFQ (ORQconst <t> [1<<8] x))
1487 (BSFQ (ORQconst <t> [1<<16] (MOVWQZX x))) => (BSFQ (ORQconst <t> [1<<16] x))
1488
1489 // Redundant sign/zero extensions
1490 // Note: see issue 21963. We have to make sure we use the right type on
1491 // the resulting extension (the outer type, not the inner type).
1492 (MOVLQSX (MOVLQSX x)) => (MOVLQSX x)
1493 (MOVLQSX (MOVWQSX x)) => (MOVWQSX x)
1494 (MOVLQSX (MOVBQSX x)) => (MOVBQSX x)
1495 (MOVWQSX (MOVWQSX x)) => (MOVWQSX x)
1496 (MOVWQSX (MOVBQSX x)) => (MOVBQSX x)
1497 (MOVBQSX (MOVBQSX x)) => (MOVBQSX x)
1498 (MOVLQZX (MOVLQZX x)) => (MOVLQZX x)
1499 (MOVLQZX (MOVWQZX x)) => (MOVWQZX x)
1500 (MOVLQZX (MOVBQZX x)) => (MOVBQZX x)
1501 (MOVWQZX (MOVWQZX x)) => (MOVWQZX x)
1502 (MOVWQZX (MOVBQZX x)) => (MOVBQZX x)
1503 (MOVBQZX (MOVBQZX x)) => (MOVBQZX x)
1504
1505 (MOVQstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Qconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
1506 && ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a) =>
1507 ((ADD|AND|OR|XOR)Qconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1508 (MOVLstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
1509 && ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a) =>
1510 ((ADD|AND|OR|XOR)Lconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1511 // Sub-word read-modify-write. The narrow store keeps only the low 8/16 bits of
1512 // the 32-bit result, so ADDB/ADDW etc. with the same constant is equivalent.
1513 // The constant is restricted to an 8-bit immediate: it keeps every form we emit
1514 // encodable as imm8 (or INC/DEC), which also avoids the 16-bit immediates that
1515 // cause length-changing-prefix stalls.
1516 (MOVWstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVWload [off] {sym} ptr2 mem)) mem)
1517 && ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a) =>
1518 ((ADD|AND|OR|XOR)Wconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1519 (MOVBstore [off] {sym} ptr a:((ADD|AND|OR|XOR)Lconst [c] l:(MOVBload [off] {sym} ptr2 mem)) mem)
1520 && ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a) =>
1521 ((ADD|AND|OR|XOR)Bconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1522
1523 // float <-> int register moves, with no conversion.
1524 // These come up when compiling math.{Float{32,64}bits,Float{32,64}frombits}.
1525 (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _)) => (MOVQf2i val)
1526 (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _)) => (MOVLf2i val)
1527 (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _)) => (MOVQi2f val)
1528 (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) => (MOVLi2f val)
1529
1530 // Other load-like ops.
1531 (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ADDQ x (MOVQf2i y))
1532 (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ADDL x (MOVLf2i y))
1533 (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (SUBQ x (MOVQf2i y))
1534 (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (SUBL x (MOVLf2i y))
1535 (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (ANDQ x (MOVQf2i y))
1536 (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (ANDL x (MOVLf2i y))
1537 ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => ( ORQ x (MOVQf2i y))
1538 ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => ( ORL x (MOVLf2i y))
1539 (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) => (XORQ x (MOVQf2i y))
1540 (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) => (XORL x (MOVLf2i y))
1541
1542 (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (ADDSD x (MOVQi2f y))
1543 (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (ADDSS x (MOVLi2f y))
1544 (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (SUBSD x (MOVQi2f y))
1545 (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (SUBSS x (MOVLi2f y))
1546 (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) => (MULSD x (MOVQi2f y))
1547 (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) => (MULSS x (MOVLi2f y))
1548
1549 // Detect FMA
1550 (ADDS(S|D) (MULS(S|D) x y) z) && buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v) => (VFMADD231S(S|D) z x y)
1551 (SUBS(S|D) (MULS(S|D) x y) z) && buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v) => (VFMSUB231S(S|D) z x y)
1552 (SUBS(S|D) x (MULS(S|D) y z)) && buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v) => (VFNMADD231S(S|D) x y z)
1553
1554 // Redirect stores to use the other register set.
1555 (MOVQstore [off] {sym} ptr (MOVQf2i val) mem) => (MOVSDstore [off] {sym} ptr val mem)
1556 (MOVLstore [off] {sym} ptr (MOVLf2i val) mem) => (MOVSSstore [off] {sym} ptr val mem)
1557 (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem) => (MOVQstore [off] {sym} ptr val mem)
1558 (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem) => (MOVLstore [off] {sym} ptr val mem)
1559
1560 (MOVSDstore [off] {sym} ptr (MOVSDconst [f]) mem) && f == f => (MOVQstore [off] {sym} ptr (MOVQconst [int64(math.Float64bits(f))]) mem)
1561 (MOVSSstore [off] {sym} ptr (MOVSSconst [f]) mem) && f == f => (MOVLstore [off] {sym} ptr (MOVLconst [int32(math.Float32bits(f))]) mem)
1562
1563 // Load args directly into the register class where it will be used.
1564 // We do this by just modifying the type of the Arg.
1565 (MOVQf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1566 (MOVLf2i <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1567 (MOVQi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1568 (MOVLi2f <t> (Arg <u> [off] {sym})) && t.Size() == u.Size() => @b.Func.Entry (Arg <t> [off] {sym})
1569
1570 // LEAQ is rematerializeable, so this helps to avoid register spill.
1571 // See issue 22947 for details
1572 (ADD(Q|L)const [off] x:(SP)) => (LEA(Q|L) [off] x)
1573
1574 // HMULx is commutative, but its first argument must go in AX.
1575 // If possible, put a rematerializeable value in the first argument slot,
1576 // to reduce the odds that another value will be have to spilled
1577 // specifically to free up AX.
1578 (HMUL(Q|L) x y) && !x.Rematerializeable() && y.Rematerializeable() => (HMUL(Q|L) y x)
1579 (HMUL(Q|L)U x y) && !x.Rematerializeable() && y.Rematerializeable() => (HMUL(Q|L)U y x)
1580
1581 // Fold loads into compares
1582 // Note: these may be undone by the flagalloc pass.
1583 (CMP(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) x) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (CMP(Q|L|W|B)load {sym} [off] ptr x mem)
1584 (CMP(Q|L|W|B) x l:(MOV(Q|L|W|B)load {sym} [off] ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (InvertFlags (CMP(Q|L|W|B)load {sym} [off] ptr x mem))
1585
1586 (CMP(Q|L)const l:(MOV(Q|L)load {sym} [off] ptr mem) [c])
1587 && l.Uses == 1
1588 && ssa.Clobber(l) =>
1589 @l.Block (CMP(Q|L)constload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
1590 (CMP(W|B)const l:(MOV(W|B)load {sym} [off] ptr mem) [c])
1591 && l.Uses == 1
1592 && ssa.Clobber(l) =>
1593 @l.Block (CMP(W|B)constload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1594
1595 (CMPQload {sym} [off] ptr (MOVQconst [c]) mem) && validVal(c) => (CMPQconstload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
1596 (CMPLload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPLconstload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
1597 (CMPWload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPWconstload {sym} [ssa.MakeValAndOff(int32(int16(c)),off)] ptr mem)
1598 (CMPBload {sym} [off] ptr (MOVLconst [c]) mem) => (CMPBconstload {sym} [ssa.MakeValAndOff(int32(int8(c)),off)] ptr mem)
1599
1600 (TEST(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) l2)
1601 && l == l2
1602 && l.Uses == 2
1603 && ssa.Clobber(l) =>
1604 @l.Block (CMP(Q|L|W|B)constload {sym} [ssa.MakeValAndOff(0, off)] ptr mem)
1605
1606 // Convert ANDload to MOVload when we can do the AND in a containing TEST op.
1607 // Only do when it's within the same block, so we don't have flags live across basic block boundaries.
1608 // See issue 44228.
1609 (TEST(Q|L) a:(AND(Q|L)load [off] {sym} x ptr mem) a) && a.Uses == 2 && a.Block == v.Block && ssa.Clobber(a) => (TEST(Q|L) (MOV(Q|L)load <a.Type> [off] {sym} ptr mem) x)
1610
1611 (MOVBload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVLconst [int32(ssa.Read8(sym, int64(off)))])
1612 (MOVWload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVLconst [int32(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1613 (MOVLload <t> [off] {sym} (SB) _) && ssa.SymIsRO(sym) && ssa.Is32BitInt(t) => (MOVLconst [int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1614 (MOVLload <t> [off] {sym} (SB) _) && ssa.SymIsRO(sym) && ssa.Is64BitInt(t) => (MOVQconst [int64(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1615 (MOVQload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(ssa.Read64(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1616 (MOVBQSXload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(int8(ssa.Read8(sym, int64(off))))])
1617 (MOVWQSXload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(int16(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
1618 (MOVLQSXload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVQconst [int64(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
1619
1620
1621 (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem) && ssa.SymIsRO(srcSym) =>
1622 (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(ssa.Read64(srcSym, int64(srcOff)+8, config.Ctxt.Arch.ByteOrder))])
1623 (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(ssa.Read64(srcSym, int64(srcOff), config.Ctxt.Arch.ByteOrder))]) mem))
1624
1625 // Arch-specific inlining for small or disjoint runtime.memmove
1626 // Match post-lowering calls, memory version.
1627 (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
1628 && sc.Val64() >= 0
1629 && ssa.IsSameCall(sym, "runtime.memmove")
1630 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
1631 && ssa.IsInlinableMemmove(dst, src, sc.Val64(), config)
1632 && ssa.Clobber(s1, s2, s3, call)
1633 => (Move [sc.Val64()] dst src mem)
1634
1635 // Match post-lowering calls, register version.
1636 (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
1637 && sz >= 0
1638 && ssa.IsSameCall(sym, "runtime.memmove")
1639 && call.Uses == 1
1640 && ssa.IsInlinableMemmove(dst, src, sz, config)
1641 && ssa.Clobber(call)
1642 => (Move [sz] dst src mem)
1643
1644 // Prefetch instructions
1645 (PrefetchCache ...) => (PrefetchT0 ...)
1646 (PrefetchCacheStreamed ...) => (PrefetchNTA ...)
1647
1648 // CPUID feature: BMI1.
1649 (AND(Q|L) x (NOT(Q|L) y)) && buildcfg.GOAMD64 >= 3 => (ANDN(Q|L) x y)
1650 (AND(Q|L) x (NEG(Q|L) x)) && buildcfg.GOAMD64 >= 3 => (BLSI(Q|L) x)
1651 (XOR(Q|L) x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (BLSMSK(Q|L) x)
1652 (AND(Q|L) <t> x (ADD(Q|L)const [-1] x)) && buildcfg.GOAMD64 >= 3 => (Select0 <t> (BLSR(Q|L) x))
1653 // eliminate TEST instruction in classical "isPowerOfTwo" check
1654 (SETEQ (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETEQ (Select1 <types.TypeFlags> blsr))
1655 (CMOVQEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQEQ x y (Select1 <types.TypeFlags> blsr))
1656 (CMOVLEQ x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLEQ x y (Select1 <types.TypeFlags> blsr))
1657 (EQ (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (EQ (Select1 <types.TypeFlags> blsr) yes no)
1658 (SETNE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (SETNE (Select1 <types.TypeFlags> blsr))
1659 (CMOVQNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVQNE x y (Select1 <types.TypeFlags> blsr))
1660 (CMOVLNE x y (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s)) => (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
1661 (NE (TEST(Q|L) s:(Select0 blsr:(BLSR(Q|L) _)) s) yes no) => (NE (Select1 <types.TypeFlags> blsr) yes no)
1662
1663 (BSWAP(Q|L) (BSWAP(Q|L) p)) => p
1664
1665 // CPUID feature: MOVBE.
1666 (MOV(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBE(Q|L)store [i] {s} p w mem)
1667 (MOVBE(Q|L)store [i] {s} p x:(BSWAP(Q|L) w) mem) && x.Uses == 1 => (MOV(Q|L)store [i] {s} p w mem)
1668 (BSWAP(Q|L) x:(MOV(Q|L)load [i] {s} p mem)) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => @x.Block (MOVBE(Q|L)load [i] {s} p mem)
1669 (BSWAP(Q|L) x:(MOVBE(Q|L)load [i] {s} p mem)) && x.Uses == 1 => @x.Block (MOV(Q|L)load [i] {s} p mem)
1670 (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 && buildcfg.GOAMD64 >= 3 => (MOVBEWstore [i] {s} p w mem)
1671 (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem) && x.Uses == 1 => (MOVWstore [i] {s} p w mem)
1672
1673 (SAR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (SARX(Q|L)load [off] {sym} ptr x mem)
1674 (SHL(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (SHLX(Q|L)load [off] {sym} ptr x mem)
1675 (SHR(Q|L) l:(MOV(Q|L)load [off] {sym} ptr mem) x) && buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (SHRX(Q|L)load [off] {sym} ptr x mem)
1676
1677 ((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVQconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
1678 ((SHL|SHR|SAR)XQload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Qconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
1679 ((SHL|SHR|SAR)XLload [off] {sym} ptr (MOVLconst [c]) mem) => ((SHL|SHR|SAR)Lconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))
1680
1681 // Convert atomic logical operations to easier ones if we don't use the result.
1682 (Select1 a:(LoweredAtomic(And64|And32|Or64|Or32) ptr val mem)) && a.Uses == 1 && ssa.Clobber(a) => ((ANDQ|ANDL|ORQ|ORL)lock ptr val mem)
1683
1684 // If we are checking the results of an add, use the flags directly from the add.
1685 // Note that this only works for EQ/NE. ADD sets the CF/OF flags differently
1686 // than TEST sets them.
1687 // Note also that a.Args[0] here refers to the post-flagify'd value.
1688 ((EQ|NE) t:(TESTQ a:(ADDQconst [c] x) a)) && t.Uses == 1 && flagify(a) => ((EQ|NE) (Select1 <types.TypeFlags> a.Args[0]))
1689 ((EQ|NE) t:(TESTL a:(ADDLconst [c] x) a)) && t.Uses == 1 && flagify(a) => ((EQ|NE) (Select1 <types.TypeFlags> a.Args[0]))
1690
1691 // If we don't use the flags any more, just use the standard op.
1692 (Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x)
1693
1694 // SIMD lowering rules
1695
1696 // Mask conversions
1697 // integers to masks
1698 (Cvt16toMask8x16 <t> x) => (VPMOVMToVec8x16 <types.TypeVec128> (KMOVWk <t> x))
1699 (Cvt32toMask8x32 <t> x) => (VPMOVMToVec8x32 <types.TypeVec256> (KMOVDk <t> x))
1700 (Cvt64toMask8x64 <t> x) => (VPMOVMToVec8x64 <types.TypeVec512> (KMOVQk <t> x))
1701
1702 (Cvt8toMask16x8 <t> x) => (VPMOVMToVec16x8 <types.TypeVec128> (KMOVBk <t> x))
1703 (Cvt16toMask16x16 <t> x) => (VPMOVMToVec16x16 <types.TypeVec256> (KMOVWk <t> x))
1704 (Cvt32toMask16x32 <t> x) => (VPMOVMToVec16x32 <types.TypeVec512> (KMOVDk <t> x))
1705
1706 (Cvt8toMask32x4 <t> x) => (VPMOVMToVec32x4 <types.TypeVec128> (KMOVBk <t> x))
1707 (Cvt8toMask32x8 <t> x) => (VPMOVMToVec32x8 <types.TypeVec256> (KMOVBk <t> x))
1708 (Cvt16toMask32x16 <t> x) => (VPMOVMToVec32x16 <types.TypeVec512> (KMOVWk <t> x))
1709
1710 (Cvt8toMask64x2 <t> x) => (VPMOVMToVec64x2 <types.TypeVec128> (KMOVBk <t> x))
1711 (Cvt8toMask64x4 <t> x) => (VPMOVMToVec64x4 <types.TypeVec256> (KMOVBk <t> x))
1712 (Cvt8toMask64x8 <t> x) => (VPMOVMToVec64x8 <types.TypeVec512> (KMOVBk <t> x))
1713
1714 // masks to integers
1715 (CvtMask8x16to16 ...) => (VPMOVMSKB128 ...)
1716 (CvtMask8x32to32 ...) => (VPMOVMSKB256 ...)
1717 (CvtMask8x64to64 x) => (KMOVQi (VPMOVVec8x64ToM <types.TypeMask> x))
1718
1719 (CvtMask16x8to8 x) => (KMOVBi (VPMOVVec16x8ToM <types.TypeMask> x))
1720 (CvtMask16x16to16 x) => (KMOVWi (VPMOVVec16x16ToM <types.TypeMask> x))
1721 (CvtMask16x32to32 x) => (KMOVDi (VPMOVVec16x32ToM <types.TypeMask> x))
1722
1723 (CvtMask32x4to8 ...) => (VMOVMSKPS128 ...)
1724 (CvtMask32x8to8 ...) => (VMOVMSKPS256 ...)
1725 (CvtMask32x16to16 x) => (KMOVWi (VPMOVVec32x16ToM <types.TypeMask> x))
1726
1727 (CvtMask64x2to8 ...) => (VMOVMSKPD128 ...)
1728 (CvtMask64x4to8 ...) => (VMOVMSKPD256 ...)
1729 (CvtMask64x8to8 x) => (KMOVBi (VPMOVVec64x8ToM <types.TypeMask> x))
1730
1731 // optimizations
1732 (MOVBstore [off] {sym} ptr (KMOVBi mask) mem) => (KMOVBstore [off] {sym} ptr mask mem)
1733 (MOVWstore [off] {sym} ptr (KMOVWi mask) mem) => (KMOVWstore [off] {sym} ptr mask mem)
1734 (MOVLstore [off] {sym} ptr (KMOVDi mask) mem) => (KMOVDstore [off] {sym} ptr mask mem)
1735 (MOVQstore [off] {sym} ptr (KMOVQi mask) mem) => (KMOVQstore [off] {sym} ptr mask mem)
1736
1737 (KMOVBk l:(MOVBload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVBload [off] {sym} ptr mem)
1738 (KMOVWk l:(MOVWload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVWload [off] {sym} ptr mem)
1739 (KMOVDk l:(MOVLload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVDload [off] {sym} ptr mem)
1740 (KMOVQk l:(MOVQload [off] {sym} ptr mem)) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l) => (KMOVQload [off] {sym} ptr mem)
1741
1742 // SIMD vector loads and stores
1743 (Load <t> ptr mem) && t.Size() == 16 => (VMOVDQUload128 ptr mem)
1744 (Store {t} ptr val mem) && t.Size() == 16 => (VMOVDQUstore128 ptr val mem)
1745
1746 (Load <t> ptr mem) && t.Size() == 32 => (VMOVDQUload256 ptr mem)
1747 (Store {t} ptr val mem) && t.Size() == 32 => (VMOVDQUstore256 ptr val mem)
1748
1749 (Load <t> ptr mem) && t.Size() == 64 => (VMOVDQUload512 ptr mem)
1750 (Store {t} ptr val mem) && t.Size() == 64 => (VMOVDQUstore512 ptr val mem)
1751
1752 // SIMD vector integer-vector-masked loads and stores.
1753 (LoadMasked32 <t> ptr mask mem) && t.Size() == 16 => (VPMASK32load128 ptr mask mem)
1754 (LoadMasked32 <t> ptr mask mem) && t.Size() == 32 => (VPMASK32load256 ptr mask mem)
1755 (LoadMasked64 <t> ptr mask mem) && t.Size() == 16 => (VPMASK64load128 ptr mask mem)
1756 (LoadMasked64 <t> ptr mask mem) && t.Size() == 32 => (VPMASK64load256 ptr mask mem)
1757
1758 (StoreMasked32 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK32store128 ptr mask val mem)
1759 (StoreMasked32 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK32store256 ptr mask val mem)
1760 (StoreMasked64 {t} ptr mask val mem) && t.Size() == 16 => (VPMASK64store128 ptr mask val mem)
1761 (StoreMasked64 {t} ptr mask val mem) && t.Size() == 32 => (VPMASK64store256 ptr mask val mem)
1762
1763 // Misc
1764 (IsZeroVec x) => (SETEQ (VPTEST x x))
1765
1766 (IsNaNFloat32x4 x) => (VCMPPS128 [3] x x)
1767 (IsNaNFloat32x8 x) => (VCMPPS256 [3] x x)
1768 (IsNaNFloat32x16 x) => (VPMOVMToVec32x16 (VCMPPS512 [3] x x))
1769 (IsNaNFloat64x2 x) => (VCMPPD128 [3] x x)
1770 (IsNaNFloat64x4 x) => (VCMPPD256 [3] x x)
1771 (IsNaNFloat64x8 x) => (VPMOVMToVec64x8 (VCMPPD512 [3] x x))
1772
1773 // SIMD vector K-masked loads and stores
1774
1775 (LoadMasked64 <t> ptr mask mem) && t.Size() == 64 => (VPMASK64load512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) mem)
1776 (LoadMasked32 <t> ptr mask mem) && t.Size() == 64 => (VPMASK32load512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) mem)
1777 (LoadMasked16 <t> ptr mask mem) && t.Size() == 64 => (VPMASK16load512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) mem)
1778 (LoadMasked8 <t> ptr mask mem) && t.Size() == 64 => (VPMASK8load512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) mem)
1779
1780 (StoreMasked64 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK64store512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) val mem)
1781 (StoreMasked32 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK32store512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) val mem)
1782 (StoreMasked16 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK16store512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) val mem)
1783 (StoreMasked8 {t} ptr mask val mem) && t.Size() == 64 => (VPMASK8store512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) val mem)
1784
1785 (ZeroSIMD <t>) && t.Size() == 16 => (Zero128 <t>)
1786 (ZeroSIMD <t>) && t.Size() == 32 => (Zero256 <t>)
1787 (ZeroSIMD <t>) && t.Size() == 64 => (Zero512 <t>)
1788
1789 // optimize x.IsNaN().Or(y.IsNaN())
1790 // do these before the mask rewrites
1791 (VPOR128 (VCMPP(S|D)128 [3] x x) (VCMPP(S|D)128 [3] y y)) => (VCMPP(S|D)128 [3] x y)
1792 (VPOR256 (VCMPP(S|D)256 [3] x x) (VCMPP(S|D)256 [3] y y)) => (VCMPP(S|D)256 [3] x y)
1793 (VPORD512 (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) (VPMOVMToVec32x16 (VCMPPS512 [3] y y))) =>
1794 (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
1795 (VPORD512 (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) (VPMOVMToVec64x8 (VCMPPD512 [3] y y))) =>
1796 (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
1797
1798 // Include these rules because you never know about rewrite order
1799 (KANDB (VCMPPD512 [3] x x) (VCMPPD512 [3] y y)) => (VCMPPD512 [3] x x) // 512 = 64x8 -> KANDB
1800 (KANDW (VCMPPS512 [3] x x) (VCMPPS512 [3] y y)) => (VCMPPS512 [3] x y) // 512 = 32x16 -> KANDW
1801
1802 // These larger simplifying rules must come before the smaller simplifying rules that might break them).
1803 // Rewrite rules for binary logical mask operations that apply to 8-bit elements (B, for bytes) of 128, 256, and 512-bit vectors
1804 (VPAND128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x16 (KANDW x y))
1805 (VPAND256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x32 (KANDD x y))
1806 (VPANDD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x64 (KANDQ x y))
1807
1808 (VPOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x16 (KORW x y))
1809 (VPOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x32 (KORD x y))
1810 (VPORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x64 (KORQ x y))
1811
1812 (VPXOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x16 (KXORW x y))
1813 (VPXOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x32 (KXORD x y))
1814 (VPXORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec8x64 (KXORQ x y))
1815
1816 // Rewrite rules for binary logical mask operations that apply to 16-bit elements (W, for words) of 128, 256, and 512-bit vectors
1817 (VPAND128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x8 (KANDB x y))
1818 (VPAND256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x16 (KANDW x y))
1819 (VPANDD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x32 (KANDD x y))
1820
1821 (VPOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x8 (KORB x y))
1822 (VPOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x16 (KORW x y))
1823 (VPORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x32 (KORD x y))
1824
1825 (VPXOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x8 (KXORB x y))
1826 (VPXOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x16 (KXORW x y))
1827 (VPXORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec16x32 (KXORD x y))
1828
1829 // Rewrite rules for binary logical mask operations that apply to 32-bit elements (D, for doublewords) of 128, 256, and 512-bit vectors
1830 (VPAND128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x4 (KANDB x y))
1831 (VPAND256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x8 (KANDB x y))
1832 (VPANDD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x16 (KANDW x y))
1833
1834 (VPOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x4 (KORB x y))
1835 (VPOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x8 (KORB x y))
1836 (VPORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x16 (KORW x y))
1837
1838 (VPXOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x4 (KXORB x y))
1839 (VPXOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x8 (KXORB x y))
1840 (VPXORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec32x16 (KXORW x y))
1841
1842 // Rewrite rules for binary logical mask operations that apply to 64-bit elements (Q, for quadwords) of 128, 256, and 512-bit vectors
1843 (VPAND128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x2 (KANDB x y))
1844 (VPAND256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x4 (KANDB x y))
1845 (VPANDD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x8 (KANDB x y))
1846
1847 (VPOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x2 (KORB x y))
1848 (VPOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x4 (KORB x y))
1849 (VPORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x8 (KORB x y))
1850
1851 (VPXOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x2 (KXORB x y))
1852 (VPXOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x4 (KXORB x y))
1853 (VPXORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VPMOVMToVec64x8 (KXORB x y))
1854
1855 (VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) => x
1856 (VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) => x
1857 (VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) => x
1858
1859 (VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) => x
1860 (VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) => x
1861 (VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) => x
1862
1863 (VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) => x
1864 (VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) => x
1865 (VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) => x
1866
1867 (VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) => x
1868 (VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) => x
1869 (VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) => x
1870
1871 (VPANDQ512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k)
1872 (VPANDQ512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k)
1873 (VPANDQ512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k)
1874 (VPANDQ512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k)
1875 (VPANDD512 x (VPMOVMToVec64x8 k)) => (VMOVDQU64Masked512 x k)
1876 (VPANDD512 x (VPMOVMToVec32x16 k)) => (VMOVDQU32Masked512 x k)
1877 (VPANDD512 x (VPMOVMToVec16x32 k)) => (VMOVDQU16Masked512 x k)
1878 (VPANDD512 x (VPMOVMToVec8x64 k)) => (VMOVDQU8Masked512 x k)
1879
1880 (VPAND128 x (VPMOVMToVec8x16 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU8Masked128 x k)
1881 (VPAND128 x (VPMOVMToVec16x8 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU16Masked128 x k)
1882 (VPAND128 x (VPMOVMToVec32x4 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU32Masked128 x k)
1883 (VPAND128 x (VPMOVMToVec64x2 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU64Masked128 x k)
1884
1885 (VPAND256 x (VPMOVMToVec8x32 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU8Masked256 x k)
1886 (VPAND256 x (VPMOVMToVec16x16 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU16Masked256 x k)
1887 (VPAND256 x (VPMOVMToVec32x8 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU32Masked256 x k)
1888 (VPAND256 x (VPMOVMToVec64x4 k)) && v.Block.CPUfeatures.HasFeature(ssa.CPUavx512) => (VMOVDQU64Masked256 x k)
1889
1890 // Insert to zero of 32/64 bit floats and ints to a zero is just MOVS[SD]
1891 (VPINSRQ128 [0] (Zero128 <t>) y) && y.Type.IsFloat() => (VMOVSDf2v <types.TypeVec128> y)
1892 (VPINSRD128 [0] (Zero128 <t>) y) && y.Type.IsFloat() => (VMOVSSf2v <types.TypeVec128> y)
1893 (VPINSRQ128 [0] (Zero128 <t>) y) && !y.Type.IsFloat() => (VMOVQ <types.TypeVec128> y)
1894 (VPINSRD128 [0] (Zero128 <t>) y) && !y.Type.IsFloat() => (VMOVD <types.TypeVec128> y)
1895
1896 // These rewrites can skip zero-extending the 8/16-bit inputs because they are
1897 // only used as the input to a broadcast; the potentially "bad" bits are ignored
1898 (VPBROADCASTB(128|256|512) x:(VPINSRB128 [0] (Zero128 <t>) y)) && x.Uses == 1 =>
1899 (VPBROADCASTB(128|256|512) (VMOVQ <types.TypeVec128> y))
1900 (VPBROADCASTW(128|256|512) x:(VPINSRW128 [0] (Zero128 <t>) y)) && x.Uses == 1 =>
1901 (VPBROADCASTW(128|256|512) (VMOVQ <types.TypeVec128> y))
1902
1903 (VMOVQ x:(MOVQload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVQload <v.Type> [off] {sym} ptr mem)
1904 (VMOVD x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVDload <v.Type> [off] {sym} ptr mem)
1905
1906 (VMOVSDf2v x:(MOVSDload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVSDload <v.Type> [off] {sym} ptr mem)
1907 (VMOVSSf2v x:(MOVSSload [off] {sym} ptr mem)) && x.Uses == 1 && ssa.Clobber(x) => @x.Block (VMOVSSload <v.Type> [off] {sym} ptr mem)
1908
1909 (VMOVSDf2v x:(MOVSDconst [c] )) => (VMOVSDconst [c] )
1910 (VMOVSSf2v x:(MOVSSconst [c] )) => (VMOVSSconst [c] )
1911
1912 (VMOVDQUload(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) => (VMOVDQUload(128|256|512) [off1+off2] {sym} ptr mem)
1913 (VMOVDQUstore(128|256|512) [off1] {sym} x:(ADDQconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) => (VMOVDQUstore(128|256|512) [off1+off2] {sym} ptr val mem)
1914 (VMOVDQUload(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) => (VMOVDQUload(128|256|512) [off1+off2] {ssa.MergeSym(sym1, sym2)} base mem)
1915 (VMOVDQUstore(128|256|512) [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem) && ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) => (VMOVDQUstore(128|256|512) [off1+off2] {ssa.MergeSym(sym1, sym2)} base val mem)
1916
1917 // Multiplication of numbers that are the power of 2 can be converted to left shift log(x)
1918 (VPMULLQ128 x (VPBROADCASTQ128 (VMOVQ (MOVQconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLQ128const [uint8(ssa.Log64(c))] x)
1919 (VPMULLQ256 x (VPBROADCASTQ256 (VMOVQ (MOVQconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLQ256const [uint8(ssa.Log64(c))] x)
1920 (VPMULLQ512 x (VPBROADCASTQ512 (VMOVQ (MOVQconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLQ512const [uint8(ssa.Log64(c))] x)
1921
1922 (VPMULLD128 x (VPBROADCASTD128 (VMOVD (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLD128const [uint8(ssa.Log32(int32(c)))] x)
1923 (VPMULLD256 x (VPBROADCASTD256 (VMOVD (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLD256const [uint8(ssa.Log32(int32(c)))] x)
1924 (VPMULLD512 x (VPBROADCASTD512 (VMOVD (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLD512const [uint8(ssa.Log32(int32(c)))] x)
1925
1926 (VPMULLW128 x (VPBROADCASTW128 (VMOVQ (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLW128const [uint8(ssa.Log16(int16(c)))] x) // use VMOVQ because VMOVW doesn't exist
1927 (VPMULLW256 x (VPBROADCASTW256 (VMOVQ (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLW256const [uint8(ssa.Log16(int16(c)))] x)
1928 (VPMULLW512 x (VPBROADCASTW512 (VMOVQ (MOVLconst [c])))) && ssa.IsPowerOfTwo(c) => (VPSLLW512const [uint8(ssa.Log16(int16(c)))] x)
1929
1930 // 2-op VPTEST optimizations
1931 (SETEQ (VPTEST x:(VPAND(128|256) j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k))
1932 (SETEQ (VPTEST x:(VPAND(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETEQ (VPTEST j k))
1933 (SETEQ (VPTEST x:(VPANDN(128|256) j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order
1934 (SETEQ (VPTEST x:(VPANDN(D|Q)512 j k) y)) && x == y && x.Uses == 2 => (SETB (VPTEST k j)) // AndNot has swapped its operand order
1935 (EQ (VPTEST x:(VPAND(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no)
1936 (EQ (VPTEST x:(VPAND(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (EQ (VPTEST j k) yes no)
1937 (EQ (VPTEST x:(VPANDN(128|256) j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order
1938 (EQ (VPTEST x:(VPANDN(D|Q)512 j k) y) yes no) && x == y && x.Uses == 2 => (ULT (VPTEST k j) yes no) // AndNot has swapped its operand order
1939
1940 // remove flags → bool → flags roundtrip
1941 // Only do it if the flag generating instruction is local otherwise the likelihood flagalloc won't undo this optimization and makes things worse are slim.
1942 (NE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1943 (NE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1944 (NE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1945 (NE t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s) yes no) && t.Block == s.Block => ((EQ|NE|LT|GT|LE|GE|UGT|ULT|UGE|ULE|EQF|NEF|UGT|UGE) flags yes no)
1946
1947 (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1948 (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1949 (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1950 (CMOVQNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVQ(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1951
1952 (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1953 (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1954 (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1955 (CMOVLNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVL(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1956
1957 (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1958 (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1959 (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1960 (CMOVWNE yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => (CMOVW(EQ|NE|LT|GT|LE|GE|HI|CS|CC|LS|EQF|NEF|GTF|GEF) yes no flags)
1961
1962 (SETNE t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
1963 (SETNE t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
1964 (SETNE t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags)) x)) && t.Block == s.Block => s
1965 (SETNE t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE|EQF|NEF|GF|GEF) flags) s)) && t.Block == s.Block => s
1966
1967 (EQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1968 (EQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1969 (EQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1970 (EQ t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s) yes no) && t.Block == s.Block => ((NE|EQ|GE|LE|GT|LT|ULE|UGE|ULT|UGT) flags yes no)
1971
1972 (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1973 (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1974 (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1975 (CMOVQEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVQ(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1976
1977 (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1978 (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1979 (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1980 (CMOVLEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVL(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1981
1982 (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1983 (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1984 (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1985 (CMOVWEQ yes no t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (CMOVW(NE|EQ|GE|LE|GT|LT|LS|CC|CS|HI) yes no flags)
1986
1987 (SETEQ t:(TESTQ x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1988 (SETEQ t:(TESTL x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1989 (SETEQ t:(TESTW x:(MOVBQZX s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags)) x)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1990 (SETEQ t:(TESTB s:(SET(EQ|NE|L|G|LE|GE|A|B|AE|BE) flags) s)) && t.Block == s.Block => (SET(NE|EQ|GE|LE|G|L|BE|AE|B|A) flags)
1991
1992 // Reinterpret int|float
1993 (I32AsF32 ...) => (MOVLi2f ...)
1994 (F32AsI32 ...) => (MOVLf2i ...)
1995 (I64AsF64 ...) => (MOVQi2f ...)
1996 (F64AsI64 ...) => (MOVQf2i ...)
1997
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