Package ppc64

import "cmd/internal/obj/ppc64"
Overview
Index

Overview ▾

Package ppc64 implements a PPC64 assembler that assembles Go asm into the corresponding PPC64 instructions as defined by the Power ISA 3.0B.

This document provides information on how to write code in Go assembler for PPC64, focusing on the differences between Go and PPC64 assembly language. It assumes some knowledge of PPC64 assembler. The original implementation of PPC64 in Go defined many opcodes that are different from PPC64 opcodes, but updates to the Go assembly language used mnemonics that are mostly similar if not identical to the PPC64 mneumonics, such as VMX and VSX instructions. Not all detail is included here; refer to the Power ISA document if interested in more detail.

Starting with Go 1.15 the Go objdump supports the -gnu option, which provides a side by side view of the Go assembler and the PPC64 assembler output. This is extremely helpful in determining what final PPC64 assembly is generated from the corresponding Go assembly.

In the examples below, the Go assembly is on the left, PPC64 assembly on the right.

1. Operand ordering

In Go asm, the last operand (right) is the target operand, but with PPC64 asm, the first operand (left) is the target. The order of the remaining operands is not consistent: in general opcodes with 3 operands that perform math or logical operations have their operands in reverse order. Opcodes for vector instructions and those with more than 3 operands usually have operands in the same order except for the target operand, which is first in PPC64 asm and last in Go asm.

Example: 

ADD R3, R4, R5		<=>	add r5, r4, r3

2. Constant operands

In Go asm, an operand that starts with '$' indicates a constant value. If the instruction using the constant has an immediate version of the opcode, then an immediate value is used with the opcode if possible.

Example: 

ADD $1, R3, R4		<=> 	addi r4, r3, 1

3. Opcodes setting condition codes

In PPC64 asm, some instructions other than compares have variations that can set the condition code where meaningful. This is indicated by adding '.' to the end of the PPC64 instruction. In Go asm, these instructions have 'CC' at the end of the opcode. The possible settings of the condition code depend on the instruction. CR0 is the default for fixed-point instructions; CR1 for floating point; CR6 for vector instructions.

Example: 

ANDCC R3, R4, R5		<=>	and. r5, r3, r4 (set CR0)

4. Loads and stores from memory

In Go asm, opcodes starting with 'MOV' indicate a load or store. When the target is a memory reference, then it is a store; when the target is a register and the source is a memory reference, then it is a load.

MOV{B,H,W,D} variations identify the size as byte, halfword, word, doubleword.

Adding 'Z' to the opcode for a load indicates zero extend; if omitted it is sign extend. Adding 'U' to a load or store indicates an update of the base register with the offset. Adding 'BR' to an opcode indicates byte-reversed load or store, or the order opposite of the expected endian order. If 'BR' is used then zero extend is assumed.

Memory references n(Ra) indicate the address in Ra + n. When used with an update form of an opcode, the value in Ra is incremented by n.

Memory references (Ra+Rb) or (Ra)(Rb) indicate the address Ra + Rb, used by indexed loads or stores. Both forms are accepted. When used with an update then the base register is updated by the value in the index register.

Examples: 

MOVD (R3), R4		<=>	ld r4,0(r3)
MOVW (R3), R4		<=>	lwa r4,0(r3)
MOVWZU 4(R3), R4		<=>	lwzu r4,4(r3)
MOVWZ (R3+R5), R4		<=>	lwzx r4,r3,r5
MOVHZ  (R3), R4		<=>	lhz r4,0(r3)
MOVHU 2(R3), R4		<=>	lhau r4,2(r3)
MOVBZ (R3), R4		<=>	lbz r4,0(r3)

MOVD R4,(R3)		<=>	std r4,0(r3)
MOVW R4,(R3)		<=>	stw r4,0(r3)
MOVW R4,(R3+R5)		<=>	stwx r4,r3,r5
MOVWU R4,4(R3)		<=>	stwu r4,4(r3)
MOVH R4,2(R3)		<=>	sth r4,2(r3)
MOVBU R4,(R3)(R5)		<=>	stbux r4,r3,r5

4. Compares

When an instruction does a compare or other operation that might result in a condition code, then the resulting condition is set in a field of the condition register. The condition register consists of 8 4-bit fields named CR0 - CR7. When a compare instruction identifies a CR then the resulting condition is set in that field to be read by a later branch or isel instruction. Within these fields, bits are set to indicate less than, greater than, or equal conditions.

Once an instruction sets a condition, then a subsequent branch, isel or other instruction can read the condition field and operate based on the bit settings.

Examples: 

CMP R3, R4			<=>	cmp r3, r4	(CR0 assumed)
CMP R3, R4, CR1		<=>	cmp cr1, r3, r4

Note that the condition register is the target operand of compare opcodes, so the remaining operands are in the same order for Go asm and PPC64 asm. When CR0 is used then it is implicit and does not need to be specified.

5. Branches

Many branches are represented as a form of the BC instruction. There are other extended opcodes to make it easier to see what type of branch is being used.

The following is a brief description of the BC instruction and its commonly used operands.

BC op1, op2, op3 

  op1: type of branch
      16 -> bctr (branch on ctr)
      12 -> bcr  (branch if cr bit is set)
      8  -> bcr+bctr (branch on ctr and cr values)
	4  -> bcr != 0 (branch if specified cr bit is not set)

	There are more combinations but these are the most common.

  op2: condition register field and condition bit

	This contains an immediate value indicating which condition field
	to read and what bits to test. Each field is 4 bits long with CR0
      at bit 0, CR1 at bit 4, etc. The value is computed as 4*CR+condition
      with these condition values:

      0 -> LT
      1 -> GT
      2 -> EQ
      3 -> OVG

	Thus 0 means test CR0 for LT, 5 means CR1 for GT, 30 means CR7 for EQ.

  op3: branch target

Examples: 

BC 12, 0, target		<=>	blt cr0, target
BC 12, 2, target		<=>	beq cr0, target
BC 12, 5, target		<=>	bgt cr1, target
BC 12, 30, target		<=>	beq cr7, target
BC 4, 6, target		<=>	bne cr1, target
BC 4, 1, target		<=>	ble cr1, target

The following extended opcodes are available for ease of use and readability:

BNE CR2, target		<=>	bne cr2, target
BEQ CR4, target		<=>	beq cr4, target
BLT target			<=>	blt target (cr0 default)
BGE CR7, target		<=>	bge cr7, target

Refer to the ISA for more information on additional values for the BC instruction, how to handle OVG information, and much more.

5. Align directive

Starting with Go 1.12, Go asm supports the PCALIGN directive, which indicates that the next instruction should be aligned to the specified value. Currently 8 and 16 are the only supported values, and a maximum of 2 NOPs will be added to align the code. That means in the case where the code is aligned to 4 but PCALIGN $16 is at that location, the code will only be aligned to 8 to avoid adding 3 NOPs.

The purpose of this directive is to improve performance for cases like loops where better alignment (8 or 16 instead of 4) might be helpful. This directive exists in PPC64 assembler and is frequently used by PPC64 assembler writers.

PCALIGN $16 PCALIGN $8

By default, functions in Go are aligned to 16 bytes, as is the case in all other compilers for PPC64. If there is a PCALIGN directive requesting alignment greater than 16, then the alignment of the containing function must be promoted to that same alignment or greater.

The behavior of PCALIGN is changed in Go 1.21 to be more straightforward to ensure the alignment required for some instructions in power10. The acceptable values are 8, 16, 32 and 64, and the use of those values will always provide the specified alignment.

6. Shift instructions

The simple scalar shifts on PPC64 expect a shift count that fits in 5 bits for 32-bit values or 6 bit for 64-bit values. If the shift count is a constant value greater than the max then the assembler sets it to the max for that size (31 for 32 bit values, 63 for 64 bit values). If the shift count is in a register, then only the low 5 or 6 bits of the register will be used as the shift count. The Go compiler will add appropriate code to compare the shift value to achieve the correct result, and the assembler does not add extra checking.

Examples: 

SRAD $8,R3,R4		=>	sradi r4,r3,8
SRD $8,R3,R4		=>	rldicl r4,r3,56,8
SLD $8,R3,R4		=>	rldicr r4,r3,8,55
SRAW $16,R4,R5		=>	srawi r5,r4,16
SRW $40,R4,R5		=>	rlwinm r5,r4,0,0,31
SLW $12,R4,R5		=>	rlwinm r5,r4,12,0,19

Some non-simple shifts have operands in the Go assembly which don't map directly onto operands in the PPC64 assembly. When an operand in a shift instruction in the Go assembly is a bit mask, that mask is represented as a start and end bit in the PPC64 assembly instead of a mask. See the ISA for more detail on these types of shifts. Here are a few examples: 

RLWMI $7,R3,$65535,R6 	=>	rlwimi r6,r3,7,16,31
RLDMI $0,R4,$7,R6 		=>	rldimi r6,r4,0,61

More recently, Go opcodes were added which map directly onto the PPC64 opcodes. It is recommended to use the newer opcodes to avoid confusion. 

RLDICL $0,R4,$15,R6		=>	rldicl r6,r4,0,15
RLDICR $0,R4,$15,R6		=>	rldicr r6.r4,0,15

Register naming

1. Special register usage in Go asm

The following registers should not be modified by user Go assembler code. 

R0: Go code expects this register to contain the value 0.
R1: Stack pointer
R2: TOC pointer when compiled with -shared or -dynlink (a.k.a position independent code)
R13: TLS pointer
R30: g (goroutine)

Register names: 

Rn is used for general purpose registers. (0-31)
Fn is used for floating point registers. (0-31)
Vn is used for vector registers. Slot 0 of Vn overlaps with Fn. (0-31)
VSn is used for vector-scalar registers. V0-V31 overlap with VS32-VS63. (0-63)
CTR represents the count register.
LR represents the link register.
CR represents the condition register
CRn represents a condition register field. (0-7)
CRnLT represents CR bit 0 of CR field n. (0-7)
CRnGT represents CR bit 1 of CR field n. (0-7)
CRnEQ represents CR bit 2 of CR field n. (0-7)
CRnSO represents CR bit 3 of CR field n. (0-7)

GOPPC64 >= power10 and its effects on Go asm

When GOPPC64=power10 is used to compile a Go program for ppc64le/linux, MOV*, FMOV*, and ADD opcodes which would require 2 or more machine instructions to emulate a 32 bit constant, or symbolic reference are implemented using prefixed instructions.

A user who wishes granular control over the generated machine code is advised to use Go asm opcodes which explicitly translate to one PPC64 machine instruction. Most common opcodes are supported.

Some examples of how pseudo-op assembly changes with GOPPC64: 

Go asm                       GOPPC64 <= power9          GOPPC64 >= power10
MOVD mypackage·foo(SB), R3   addis r2, r3, ...          pld r3, ...
                             ld    r3, r3, ...

MOVD 131072(R3), R4          addis r31, r4, 2           pld r4, 131072(r3)
                             ld    r4, 0(R3)

ADD $131073, R3              lis  r31, 2                paddi r3, r3, 131073
                             addi r31, 1
                             add  r3,r31,r3

MOVD $131073, R3             lis  r3, 2                 pli r3, 131073
                             addi r3, 1

MOVD $mypackage·foo(SB), R3  addis r2, r3, ...          pla r3, ...
                             addi  r3, r3, ...

Index ▾

Constants
Variables
func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32
func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32
func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32
func AOP_IR(op uint32, d uint32, simm uint32) uint32
func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32
func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32
func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32
func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32
func AOP_MDS(op, to, from, rsh, m uint32) uint32
func AOP_PFX_00_8LS(r, ie uint32) uint32
func AOP_PFX_10_MLS(r, ie uint32) uint32
func AOP_RR(op uint32, d uint32, a uint32) uint32
func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32
func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32
func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32
func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32
func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32
func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32
func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32
func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32
func ConstantToCRbit(c int64) (int16, bool)
func DRconv(a int) string
func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32
func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32
func NeedTOCpointer(ctxt *obj.Link) bool
func OPCC(o uint32, xo uint32, rc uint32) uint32
func OPDQ(o uint32, xo uint32, oe uint32) uint32
func OPMD(o, xo, rc uint32) uint32
func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32
func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32
func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32
func OPVXX1(o uint32, xo uint32, oe uint32) uint32
func OPVXX2(o uint32, xo uint32, oe uint32) uint32
func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32
func OPVXX3(o uint32, xo uint32, oe uint32) uint32
func OPVXX4(o uint32, xo uint32, oe uint32) uint32
func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32
func OP_BCR(op uint32, bo uint32, bi uint32) uint32
func OP_BR(op uint32, li uint32, aa uint32) uint32
func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32
type Optab
type PrefixableOptab

Package files

a.out.go anames.go anames9.go asm9.go asm9_gtables.go doc.go list9.go obj9.go

Constants

* powerpc 64 

const (
    NSNAME = 8
    NSYM   = 50
    NREG   = 32 /* number of general registers */
    NFREG  = 32 /* number of floating point registers */
)
const (
    /* RBasePPC64 = 4096 */
    /* R0=4096 ... R31=4127 */
    REG_R0 = obj.RBasePPC64 + iota
    REG_R1
    REG_R2
    REG_R3
    REG_R4
    REG_R5
    REG_R6
    REG_R7
    REG_R8
    REG_R9
    REG_R10
    REG_R11
    REG_R12
    REG_R13
    REG_R14
    REG_R15
    REG_R16
    REG_R17
    REG_R18
    REG_R19
    REG_R20
    REG_R21
    REG_R22
    REG_R23
    REG_R24
    REG_R25
    REG_R26
    REG_R27
    REG_R28
    REG_R29
    REG_R30
    REG_R31

    // CR bits. Use Book 1, chapter 2 naming for bits. Keep aligned to 32
    REG_CR0LT
    REG_CR0GT
    REG_CR0EQ
    REG_CR0SO
    REG_CR1LT
    REG_CR1GT
    REG_CR1EQ
    REG_CR1SO
    REG_CR2LT
    REG_CR2GT
    REG_CR2EQ
    REG_CR2SO
    REG_CR3LT
    REG_CR3GT
    REG_CR3EQ
    REG_CR3SO
    REG_CR4LT
    REG_CR4GT
    REG_CR4EQ
    REG_CR4SO
    REG_CR5LT
    REG_CR5GT
    REG_CR5EQ
    REG_CR5SO
    REG_CR6LT
    REG_CR6GT
    REG_CR6EQ
    REG_CR6SO
    REG_CR7LT
    REG_CR7GT
    REG_CR7EQ
    REG_CR7SO

    /* Align FPR and VSR vectors such that when masked with 0x3F they produce
       an equivalent VSX register. */
    /* F0=4160 ... F31=4191 */
    REG_F0
    REG_F1
    REG_F2
    REG_F3
    REG_F4
    REG_F5
    REG_F6
    REG_F7
    REG_F8
    REG_F9
    REG_F10
    REG_F11
    REG_F12
    REG_F13
    REG_F14
    REG_F15
    REG_F16
    REG_F17
    REG_F18
    REG_F19
    REG_F20
    REG_F21
    REG_F22
    REG_F23
    REG_F24
    REG_F25
    REG_F26
    REG_F27
    REG_F28
    REG_F29
    REG_F30
    REG_F31

    /* V0=4192 ... V31=4223 */
    REG_V0
    REG_V1
    REG_V2
    REG_V3
    REG_V4
    REG_V5
    REG_V6
    REG_V7
    REG_V8
    REG_V9
    REG_V10
    REG_V11
    REG_V12
    REG_V13
    REG_V14
    REG_V15
    REG_V16
    REG_V17
    REG_V18
    REG_V19
    REG_V20
    REG_V21
    REG_V22
    REG_V23
    REG_V24
    REG_V25
    REG_V26
    REG_V27
    REG_V28
    REG_V29
    REG_V30
    REG_V31

    /* VS0=4224 ... VS63=4287 */
    REG_VS0
    REG_VS1
    REG_VS2
    REG_VS3
    REG_VS4
    REG_VS5
    REG_VS6
    REG_VS7
    REG_VS8
    REG_VS9
    REG_VS10
    REG_VS11
    REG_VS12
    REG_VS13
    REG_VS14
    REG_VS15
    REG_VS16
    REG_VS17
    REG_VS18
    REG_VS19
    REG_VS20
    REG_VS21
    REG_VS22
    REG_VS23
    REG_VS24
    REG_VS25
    REG_VS26
    REG_VS27
    REG_VS28
    REG_VS29
    REG_VS30
    REG_VS31
    REG_VS32
    REG_VS33
    REG_VS34
    REG_VS35
    REG_VS36
    REG_VS37
    REG_VS38
    REG_VS39
    REG_VS40
    REG_VS41
    REG_VS42
    REG_VS43
    REG_VS44
    REG_VS45
    REG_VS46
    REG_VS47
    REG_VS48
    REG_VS49
    REG_VS50
    REG_VS51
    REG_VS52
    REG_VS53
    REG_VS54
    REG_VS55
    REG_VS56
    REG_VS57
    REG_VS58
    REG_VS59
    REG_VS60
    REG_VS61
    REG_VS62
    REG_VS63

    REG_CR0
    REG_CR1
    REG_CR2
    REG_CR3
    REG_CR4
    REG_CR5
    REG_CR6
    REG_CR7

    // MMA accumulator registers, these shadow VSR 0-31
    // e.g MMAx shadows VSRx*4-VSRx*4+3 or
    //     MMA0 shadows VSR0-VSR3
    REG_A0
    REG_A1
    REG_A2
    REG_A3
    REG_A4
    REG_A5
    REG_A6
    REG_A7

    REG_MSR
    REG_FPSCR
    REG_CR

    REG_SPECIAL = REG_CR0

    REG_CRBIT0 = REG_CR0LT // An alias for a Condition Register bit 0

    REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers

    REG_XER = REG_SPR0 + 1
    REG_LR  = REG_SPR0 + 8
    REG_CTR = REG_SPR0 + 9

    REGZERO = REG_R0 /* set to zero */
    REGSP   = REG_R1
    REGSB   = REG_R2
    REGRET  = REG_R3
    REGARG  = -1      /* -1 disables passing the first argument in register */
    REGRT1  = REG_R20 /* reserved for runtime, duffzero and duffcopy */
    REGRT2  = REG_R21 /* reserved for runtime, duffcopy */
    REGMIN  = REG_R7  /* register variables allocated from here to REGMAX */
    REGCTXT = REG_R11 /* context for closures */
    REGTLS  = REG_R13 /* C ABI TLS base pointer */
    REGMAX  = REG_R27
    REGEXT  = REG_R30 /* external registers allocated from here down */
    REGG    = REG_R30 /* G */
    REGTMP  = REG_R31 /* used by the linker */
    FREGRET = REG_F0
    FREGMIN = REG_F17 /* first register variable */
    FREGMAX = REG_F26 /* last register variable for 9g only */
    FREGEXT = REG_F26 /* first external register */
)
const (
    /* mark flags */
    LABEL    = 1 << 0
    LEAF     = 1 << 1
    FLOAT    = 1 << 2
    BRANCH   = 1 << 3
    LOAD     = 1 << 4
    FCMP     = 1 << 5
    SYNC     = 1 << 6
    LIST     = 1 << 7
    FOLL     = 1 << 8
    NOSCHED  = 1 << 9
    PFX_X64B = 1 << 10 // A prefixed instruction crossing a 64B boundary
)
const (
    BI_CR0 = 0
    BI_CR1 = 4
    BI_CR2 = 8
    BI_CR3 = 12
    BI_CR4 = 16
    BI_CR5 = 20
    BI_CR6 = 24
    BI_CR7 = 28
    BI_LT  = 0
    BI_GT  = 1
    BI_EQ  = 2
    BI_FU  = 3
)
const (
    BO_ALWAYS  = 20 // branch unconditionally
    BO_BCTR    = 16 // decrement ctr, branch on ctr != 0
    BO_NOTBCTR = 18 // decrement ctr, branch on ctr == 0
    BO_BCR     = 12 // branch on cr value
    BO_BCRBCTR = 8  // decrement ctr, branch on ctr != 0 and cr value
    BO_NOTBCR  = 4  // branch on not cr value
)
const (
    C_COND_LT = iota // 0 result is negative
    C_COND_GT        // 1 result is positive
    C_COND_EQ        // 2 result is zero
    C_COND_SO        // 3 summary overflow or FP compare w/ NaN
)
const (
    C_NONE     = iota
    C_REGP     /* An even numbered gpr which can be used a gpr pair argument */
    C_REG      /* Any gpr register */
    C_FREGP    /* An even numbered fpr which can be used a fpr pair argument */
    C_FREG     /* Any fpr register */
    C_VREG     /* Any vector register */
    C_VSREGP   /* An even numbered vsx register which can be used as a vsx register pair argument */
    C_VSREG    /* Any vector-scalar register */
    C_CREG     /* The condition registor (CR) */
    C_CRBIT    /* A single bit of the CR register (0-31) */
    C_SPR      /* special processor register */
    C_AREG     /* MMA accumulator register */
    C_ZCON     /* The constant zero */
    C_U1CON    /* 1 bit unsigned constant */
    C_U2CON    /* 2 bit unsigned constant */
    C_U3CON    /* 3 bit unsigned constant */
    C_U4CON    /* 4 bit unsigned constant */
    C_U5CON    /* 5 bit unsigned constant */
    C_U8CON    /* 8 bit unsigned constant */
    C_U15CON   /* 15 bit unsigned constant */
    C_S16CON   /* 16 bit signed constant */
    C_U16CON   /* 16 bit unsigned constant */
    C_16CON    /* Any constant which fits into 16 bits. Can be signed or unsigned */
    C_U31CON   /* 31 bit unsigned constant */
    C_S32CON   /* 32 bit signed constant */
    C_U32CON   /* 32 bit unsigned constant */
    C_32CON    /* Any constant which fits into 32 bits. Can be signed or unsigned */
    C_S34CON   /* 34 bit signed constant */
    C_64CON    /* Any constant which fits into 64 bits. Can be signed or unsigned */
    C_SACON    /* $n(REG) where n <= int16 */
    C_LACON    /* $n(REG) where n <= int32 */
    C_DACON    /* $n(REG) where n <= int64 */
    C_BRA      /* A short offset argument to a branching instruction */
    C_BRAPIC   /* Like C_BRA, but requires an extra NOP for potential TOC restore by the linker. */
    C_ZOREG    /* An $0+reg memory op */
    C_SOREG    /* An $n+reg memory arg where n is a 16 bit signed offset */
    C_LOREG    /* An $n+reg memory arg where n is a 32 bit signed offset */
    C_XOREG    /* An reg+reg memory arg */
    C_FPSCR    /* The fpscr register */
    C_LR       /* The link register */
    C_CTR      /* The count register */
    C_ANY      /* Any argument */
    C_GOK      /* A non-matched argument */
    C_ADDR     /* A symbolic memory location */
    C_TLS_LE   /* A thread local, local-exec, type memory arg */
    C_TLS_IE   /* A thread local, initial-exec, type memory arg */
    C_TEXTSIZE /* An argument with Type obj.TYPE_TEXTSIZE */

    C_NCLASS /* must be the last */
)
const (
    AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
    AADDCC
    AADDIS
    AADDV
    AADDVCC
    AADDC
    AADDCCC
    AADDCV
    AADDCVCC
    AADDME
    AADDMECC
    AADDMEVCC
    AADDMEV
    AADDE
    AADDECC
    AADDEVCC
    AADDEV
    AADDZE
    AADDZECC
    AADDZEVCC
    AADDZEV
    AADDEX
    AAND
    AANDCC
    AANDN
    AANDNCC
    AANDISCC
    ABC
    ABCL
    ABEQ
    ABGE // not LT = G/E/U
    ABGT
    ABLE // not GT = L/E/U
    ABLT
    ABNE  // not EQ = L/G/U
    ABVC  // Branch if float not unordered (also branch on not summary overflow)
    ABVS  // Branch if float unordered (also branch on summary overflow)
    ABDNZ // Decrement CTR, and branch if CTR != 0
    ABDZ  // Decrement CTR, and branch if CTR == 0
    ACMP
    ACMPU
    ACMPEQB
    ACNTLZW
    ACNTLZWCC
    ACRAND
    ACRANDN
    ACREQV
    ACRNAND
    ACRNOR
    ACROR
    ACRORN
    ACRXOR
    ADADD
    ADADDQ
    ADCMPO
    ADCMPOQ
    ADCMPU
    ADCMPUQ
    ADDIV
    ADDIVQ
    ADIVW
    ADIVWCC
    ADIVWVCC
    ADIVWV
    ADIVWU
    ADIVWUCC
    ADIVWUVCC
    ADIVWUV
    ADMUL
    ADMULQ
    ADSUB
    ADSUBQ
    AMODUD
    AMODUW
    AMODSD
    AMODSW
    AEQV
    AEQVCC
    AEXTSB
    AEXTSBCC
    AEXTSH
    AEXTSHCC
    AFABS
    AFABSCC
    AFADD
    AFADDCC
    AFADDS
    AFADDSCC
    AFCMPO
    AFCMPU
    AFCTIW
    AFCTIWCC
    AFCTIWZ
    AFCTIWZCC
    AFDIV
    AFDIVCC
    AFDIVS
    AFDIVSCC
    AFMADD
    AFMADDCC
    AFMADDS
    AFMADDSCC
    AFMOVD
    AFMOVDCC
    AFMOVDU
    AFMOVS
    AFMOVSU
    AFMOVSX
    AFMOVSZ
    AFMSUB
    AFMSUBCC
    AFMSUBS
    AFMSUBSCC
    AFMUL
    AFMULCC
    AFMULS
    AFMULSCC
    AFNABS
    AFNABSCC
    AFNEG
    AFNEGCC
    AFNMADD
    AFNMADDCC
    AFNMADDS
    AFNMADDSCC
    AFNMSUB
    AFNMSUBCC
    AFNMSUBS
    AFNMSUBSCC
    AFRSP
    AFRSPCC
    AFSUB
    AFSUBCC
    AFSUBS
    AFSUBSCC
    AISEL
    AMOVMW
    ALBAR
    ALHAR
    ALSW
    ALWAR
    ALWSYNC
    AMOVDBR
    AMOVWBR
    AMOVB
    AMOVBU
    AMOVBZ
    AMOVBZU
    AMOVH
    AMOVHBR
    AMOVHU
    AMOVHZ
    AMOVHZU
    AMOVW
    AMOVWU
    AMOVFL
    AMOVCRFS
    AMTFSB0
    AMTFSB0CC
    AMTFSB1
    AMTFSB1CC
    AMULHW
    AMULHWCC
    AMULHWU
    AMULHWUCC
    AMULLW
    AMULLWCC
    AMULLWVCC
    AMULLWV
    ANAND
    ANANDCC
    ANEG
    ANEGCC
    ANEGVCC
    ANEGV
    ANOR
    ANORCC
    AOR
    AORCC
    AORN
    AORNCC
    AORIS
    AREM
    AREMU
    ARFI
    ARLWMI
    ARLWMICC
    ARLWNM
    ARLWNMCC
    ACLRLSLWI
    ASLW
    ASLWCC
    ASRW
    ASRAW
    ASRAWCC
    ASRWCC
    ASTBCCC
    ASTHCCC
    ASTSW
    ASTWCCC
    ASUB
    ASUBCC
    ASUBVCC
    ASUBC
    ASUBCCC
    ASUBCV
    ASUBCVCC
    ASUBME
    ASUBMECC
    ASUBMEVCC
    ASUBMEV
    ASUBV
    ASUBE
    ASUBECC
    ASUBEV
    ASUBEVCC
    ASUBZE
    ASUBZECC
    ASUBZEVCC
    ASUBZEV
    ASYNC
    AXOR
    AXORCC
    AXORIS

    ADCBF
    ADCBI
    ADCBST
    ADCBT
    ADCBTST
    ADCBZ
    AEIEIO
    AICBI
    AISYNC
    APTESYNC
    ATLBIE
    ATLBIEL
    ATLBSYNC
    ATW

    ASYSCALL
    AWORD

    ARFCI

    AFCPSGN
    AFCPSGNCC
    /* optional on 32-bit */
    AFRES
    AFRESCC
    AFRIM
    AFRIMCC
    AFRIP
    AFRIPCC
    AFRIZ
    AFRIZCC
    AFRIN
    AFRINCC
    AFRSQRTE
    AFRSQRTECC
    AFSEL
    AFSELCC
    AFSQRT
    AFSQRTCC
    AFSQRTS
    AFSQRTSCC

    ACNTLZD
    ACNTLZDCC
    ACMPW /* CMP with L=0 */
    ACMPWU
    ACMPB
    AFTDIV
    AFTSQRT
    ADIVD
    ADIVDCC
    ADIVDE
    ADIVDECC
    ADIVDEU
    ADIVDEUCC
    ADIVDVCC
    ADIVDV
    ADIVDU
    ADIVDUCC
    ADIVDUVCC
    ADIVDUV
    AEXTSW
    AEXTSWCC
    /* AFCFIW; AFCFIWCC */
    AFCFID
    AFCFIDCC
    AFCFIDU
    AFCFIDUCC
    AFCFIDS
    AFCFIDSCC
    AFCTID
    AFCTIDCC
    AFCTIDZ
    AFCTIDZCC
    ALDAR
    AMOVD
    AMOVDU
    AMOVWZ
    AMOVWZU
    AMULHD
    AMULHDCC
    AMULHDU
    AMULHDUCC
    AMULLD
    AMULLDCC
    AMULLDVCC
    AMULLDV
    ARFID
    ARLDMI
    ARLDMICC
    ARLDIMI
    ARLDIMICC
    ARLDC
    ARLDCCC
    ARLDCR
    ARLDCRCC
    ARLDICR
    ARLDICRCC
    ARLDCL
    ARLDCLCC
    ARLDICL
    ARLDICLCC
    ARLDIC
    ARLDICCC
    ACLRLSLDI
    AROTL
    AROTLW
    ASLBIA
    ASLBIE
    ASLBMFEE
    ASLBMFEV
    ASLBMTE
    ASLD
    ASLDCC
    ASRD
    ASRAD
    ASRADCC
    ASRDCC
    AEXTSWSLI
    AEXTSWSLICC
    ASTDCCC
    ATD
    ASETB

    /* 64-bit pseudo operation */
    ADWORD
    AREMD
    AREMDU

    /* more 64-bit operations */
    AHRFID
    APOPCNTD
    APOPCNTW
    APOPCNTB
    ACNTTZW
    ACNTTZWCC
    ACNTTZD
    ACNTTZDCC
    ACOPY
    APASTECC
    ADARN
    AMADDHD
    AMADDHDU
    AMADDLD

    /* Vector */
    ALVEBX
    ALVEHX
    ALVEWX
    ALVX
    ALVXL
    ALVSL
    ALVSR
    ASTVEBX
    ASTVEHX
    ASTVEWX
    ASTVX
    ASTVXL
    AVAND
    AVANDC
    AVNAND
    AVOR
    AVORC
    AVNOR
    AVXOR
    AVEQV
    AVADDUM
    AVADDUBM
    AVADDUHM
    AVADDUWM
    AVADDUDM
    AVADDUQM
    AVADDCU
    AVADDCUQ
    AVADDCUW
    AVADDUS
    AVADDUBS
    AVADDUHS
    AVADDUWS
    AVADDSS
    AVADDSBS
    AVADDSHS
    AVADDSWS
    AVADDE
    AVADDEUQM
    AVADDECUQ
    AVSUBUM
    AVSUBUBM
    AVSUBUHM
    AVSUBUWM
    AVSUBUDM
    AVSUBUQM
    AVSUBCU
    AVSUBCUQ
    AVSUBCUW
    AVSUBUS
    AVSUBUBS
    AVSUBUHS
    AVSUBUWS
    AVSUBSS
    AVSUBSBS
    AVSUBSHS
    AVSUBSWS
    AVSUBE
    AVSUBEUQM
    AVSUBECUQ
    AVMULESB
    AVMULOSB
    AVMULEUB
    AVMULOUB
    AVMULESH
    AVMULOSH
    AVMULEUH
    AVMULOUH
    AVMULESW
    AVMULOSW
    AVMULEUW
    AVMULOUW
    AVMULUWM
    AVPMSUM
    AVPMSUMB
    AVPMSUMH
    AVPMSUMW
    AVPMSUMD
    AVMSUMUDM
    AVR
    AVRLB
    AVRLH
    AVRLW
    AVRLD
    AVS
    AVSLB
    AVSLH
    AVSLW
    AVSL
    AVSLO
    AVSRB
    AVSRH
    AVSRW
    AVSR
    AVSRO
    AVSLD
    AVSRD
    AVSA
    AVSRAB
    AVSRAH
    AVSRAW
    AVSRAD
    AVSOI
    AVSLDOI
    AVCLZ
    AVCLZB
    AVCLZH
    AVCLZW
    AVCLZD
    AVPOPCNT
    AVPOPCNTB
    AVPOPCNTH
    AVPOPCNTW
    AVPOPCNTD
    AVCMPEQ
    AVCMPEQUB
    AVCMPEQUBCC
    AVCMPEQUH
    AVCMPEQUHCC
    AVCMPEQUW
    AVCMPEQUWCC
    AVCMPEQUD
    AVCMPEQUDCC
    AVCMPGT
    AVCMPGTUB
    AVCMPGTUBCC
    AVCMPGTUH
    AVCMPGTUHCC
    AVCMPGTUW
    AVCMPGTUWCC
    AVCMPGTUD
    AVCMPGTUDCC
    AVCMPGTSB
    AVCMPGTSBCC
    AVCMPGTSH
    AVCMPGTSHCC
    AVCMPGTSW
    AVCMPGTSWCC
    AVCMPGTSD
    AVCMPGTSDCC
    AVCMPNEZB
    AVCMPNEZBCC
    AVCMPNEB
    AVCMPNEBCC
    AVCMPNEH
    AVCMPNEHCC
    AVCMPNEW
    AVCMPNEWCC
    AVPERM
    AVPERMXOR
    AVPERMR
    AVBPERMQ
    AVBPERMD
    AVSEL
    AVSPLTB
    AVSPLTH
    AVSPLTW
    AVSPLTISB
    AVSPLTISH
    AVSPLTISW
    AVCIPH
    AVCIPHER
    AVCIPHERLAST
    AVNCIPH
    AVNCIPHER
    AVNCIPHERLAST
    AVSBOX
    AVSHASIGMA
    AVSHASIGMAW
    AVSHASIGMAD
    AVMRGEW
    AVMRGOW
    AVCLZLSBB
    AVCTZLSBB

    /* VSX */
    ALXV
    ALXVL
    ALXVLL
    ALXVD2X
    ALXVW4X
    ALXVH8X
    ALXVB16X
    ALXVX
    ALXVDSX
    ASTXV
    ASTXVL
    ASTXVLL
    ASTXVD2X
    ASTXVW4X
    ASTXVH8X
    ASTXVB16X
    ASTXVX
    ALXSDX
    ASTXSDX
    ALXSIWAX
    ALXSIWZX
    ASTXSIWX
    AMFVSRD
    AMFFPRD
    AMFVRD
    AMFVSRWZ
    AMFVSRLD
    AMTVSRD
    AMTFPRD
    AMTVRD
    AMTVSRWA
    AMTVSRWZ
    AMTVSRDD
    AMTVSRWS
    AXXLAND
    AXXLANDC
    AXXLEQV
    AXXLNAND
    AXXLOR
    AXXLORC
    AXXLNOR
    AXXLORQ
    AXXLXOR
    AXXSEL
    AXXMRGHW
    AXXMRGLW
    AXXSPLTW
    AXXSPLTIB
    AXXPERM
    AXXPERMDI
    AXXSLDWI
    AXXBRQ
    AXXBRD
    AXXBRW
    AXXBRH
    AXSCVDPSP
    AXSCVSPDP
    AXSCVDPSPN
    AXSCVSPDPN
    AXVCVDPSP
    AXVCVSPDP
    AXSCVDPSXDS
    AXSCVDPSXWS
    AXSCVDPUXDS
    AXSCVDPUXWS
    AXSCVSXDDP
    AXSCVUXDDP
    AXSCVSXDSP
    AXSCVUXDSP
    AXVCVDPSXDS
    AXVCVDPSXWS
    AXVCVDPUXDS
    AXVCVDPUXWS
    AXVCVSPSXDS
    AXVCVSPSXWS
    AXVCVSPUXDS
    AXVCVSPUXWS
    AXVCVSXDDP
    AXVCVSXWDP
    AXVCVUXDDP
    AXVCVUXWDP
    AXVCVSXDSP
    AXVCVSXWSP
    AXVCVUXDSP
    AXVCVUXWSP
    AXSMAXJDP
    AXSMINJDP
    ALASTAOUT // The last instruction in this list. Also the first opcode generated by ppc64map.

    // aliases
    ABR   = obj.AJMP
    ABL   = obj.ACALL
    ALAST = ALASTGEN // The final enumerated instruction value + 1. This is used to size the oprange table.
)
const (
    // R bit option in prefixed load/store/add D-form operations
    PFX_R_ABS   = 0 // Offset is absolute
    PFX_R_PCREL = 1 // Offset is relative to PC, RA should be 0
)
const (
    /* each rhs is OPVCC(_, _, _, _) */
    OP_ADD      = 31<<26 | 266<<1 | 0<<10 | 0
    OP_ADDI     = 14<<26 | 0<<1 | 0<<10 | 0
    OP_ADDIS    = 15<<26 | 0<<1 | 0<<10 | 0
    OP_ANDI     = 28<<26 | 0<<1 | 0<<10 | 0
    OP_EXTSB    = 31<<26 | 954<<1 | 0<<10 | 0
    OP_EXTSH    = 31<<26 | 922<<1 | 0<<10 | 0
    OP_EXTSW    = 31<<26 | 986<<1 | 0<<10 | 0
    OP_ISEL     = 31<<26 | 15<<1 | 0<<10 | 0
    OP_MCRF     = 19<<26 | 0<<1 | 0<<10 | 0
    OP_MCRFS    = 63<<26 | 64<<1 | 0<<10 | 0
    OP_MCRXR    = 31<<26 | 512<<1 | 0<<10 | 0
    OP_MFCR     = 31<<26 | 19<<1 | 0<<10 | 0
    OP_MFFS     = 63<<26 | 583<<1 | 0<<10 | 0
    OP_MFSPR    = 31<<26 | 339<<1 | 0<<10 | 0
    OP_MFSR     = 31<<26 | 595<<1 | 0<<10 | 0
    OP_MFSRIN   = 31<<26 | 659<<1 | 0<<10 | 0
    OP_MTCRF    = 31<<26 | 144<<1 | 0<<10 | 0
    OP_MTFSF    = 63<<26 | 711<<1 | 0<<10 | 0
    OP_MTFSFI   = 63<<26 | 134<<1 | 0<<10 | 0
    OP_MTSPR    = 31<<26 | 467<<1 | 0<<10 | 0
    OP_MTSR     = 31<<26 | 210<<1 | 0<<10 | 0
    OP_MTSRIN   = 31<<26 | 242<<1 | 0<<10 | 0
    OP_MULLW    = 31<<26 | 235<<1 | 0<<10 | 0
    OP_MULLD    = 31<<26 | 233<<1 | 0<<10 | 0
    OP_OR       = 31<<26 | 444<<1 | 0<<10 | 0
    OP_ORI      = 24<<26 | 0<<1 | 0<<10 | 0
    OP_ORIS     = 25<<26 | 0<<1 | 0<<10 | 0
    OP_XORI     = 26<<26 | 0<<1 | 0<<10 | 0
    OP_XORIS    = 27<<26 | 0<<1 | 0<<10 | 0
    OP_RLWINM   = 21<<26 | 0<<1 | 0<<10 | 0
    OP_RLWNM    = 23<<26 | 0<<1 | 0<<10 | 0
    OP_SUBF     = 31<<26 | 40<<1 | 0<<10 | 0
    OP_RLDIC    = 30<<26 | 4<<1 | 0<<10 | 0
    OP_RLDICR   = 30<<26 | 2<<1 | 0<<10 | 0
    OP_RLDICL   = 30<<26 | 0<<1 | 0<<10 | 0
    OP_RLDCL    = 30<<26 | 8<<1 | 0<<10 | 0
    OP_EXTSWSLI = 31<<26 | 445<<2
    OP_SETB     = 31<<26 | 128<<1
)
const (
    D_FORM = iota
    DS_FORM
)
const (
    AXXSETACCZ = ALASTAOUT + iota
    AXXMTACC
    AXXMFACC
    AXXGENPCVWM
    AXXGENPCVHM
    AXXGENPCVDM
    AXXGENPCVBM
    AXVTLSBB
    AXVI8GER4SPP
    AXVI8GER4PP
    AXVI8GER4
    AXVI4GER8PP
    AXVI4GER8
    AXVI16GER2SPP
    AXVI16GER2S
    AXVI16GER2PP
    AXVI16GER2
    AXVF64GERPP
    AXVF64GERPN
    AXVF64GERNP
    AXVF64GERNN
    AXVF64GER
    AXVF32GERPP
    AXVF32GERPN
    AXVF32GERNP
    AXVF32GERNN
    AXVF32GER
    AXVF16GER2PP
    AXVF16GER2PN
    AXVF16GER2NP
    AXVF16GER2NN
    AXVF16GER2
    AXVCVSPBF16
    AXVCVBF16SPN
    AXVBF16GER2PP
    AXVBF16GER2PN
    AXVBF16GER2NP
    AXVBF16GER2NN
    AXVBF16GER2
    AXSMINCQP
    AXSMAXCQP
    AXSCVUQQP
    AXSCVSQQP
    AXSCVQPUQZ
    AXSCVQPSQZ
    AXSCMPGTQP
    AXSCMPGEQP
    AXSCMPEQQP
    AVSTRIHRCC
    AVSTRIHR
    AVSTRIHLCC
    AVSTRIHL
    AVSTRIBRCC
    AVSTRIBR
    AVSTRIBLCC
    AVSTRIBL
    AVSRQ
    AVSRDBI
    AVSRAQ
    AVSLQ
    AVSLDBI
    AVRLQNM
    AVRLQMI
    AVRLQ
    AVPEXTD
    AVPDEPD
    AVMULOUD
    AVMULOSD
    AVMULLD
    AVMULHUW
    AVMULHUD
    AVMULHSW
    AVMULHSD
    AVMULEUD
    AVMULESD
    AVMSUMCUD
    AVMODUW
    AVMODUQ
    AVMODUD
    AVMODSW
    AVMODSQ
    AVMODSD
    AVINSWVRX
    AVINSWVLX
    AVINSWRX
    AVINSWLX
    AVINSW
    AVINSHVRX
    AVINSHVLX
    AVINSHRX
    AVINSHLX
    AVINSDRX
    AVINSDLX
    AVINSD
    AVINSBVRX
    AVINSBVLX
    AVINSBRX
    AVINSBLX
    AVGNB
    AVEXTSD2Q
    AVEXTRACTWM
    AVEXTRACTQM
    AVEXTRACTHM
    AVEXTRACTDM
    AVEXTRACTBM
    AVEXTDUWVRX
    AVEXTDUWVLX
    AVEXTDUHVRX
    AVEXTDUHVLX
    AVEXTDUBVRX
    AVEXTDUBVLX
    AVEXTDDVRX
    AVEXTDDVLX
    AVEXPANDWM
    AVEXPANDQM
    AVEXPANDHM
    AVEXPANDDM
    AVEXPANDBM
    AVDIVUW
    AVDIVUQ
    AVDIVUD
    AVDIVSW
    AVDIVSQ
    AVDIVSD
    AVDIVEUW
    AVDIVEUQ
    AVDIVEUD
    AVDIVESW
    AVDIVESQ
    AVDIVESD
    AVCTZDM
    AVCNTMBW
    AVCNTMBH
    AVCNTMBD
    AVCNTMBB
    AVCMPUQ
    AVCMPSQ
    AVCMPGTUQCC
    AVCMPGTUQ
    AVCMPGTSQCC
    AVCMPGTSQ
    AVCMPEQUQCC
    AVCMPEQUQ
    AVCLZDM
    AVCLRRB
    AVCLRLB
    AVCFUGED
    ASTXVRWX
    ASTXVRHX
    ASTXVRDX
    ASTXVRBX
    ASTXVPX
    ASTXVP
    ASETNBCR
    ASETNBC
    ASETBCR
    ASETBC
    APEXTD
    APDEPD
    AMTVSRWM
    AMTVSRQM
    AMTVSRHM
    AMTVSRDM
    AMTVSRBMI
    AMTVSRBM
    ALXVRWX
    ALXVRHX
    ALXVRDX
    ALXVRBX
    ALXVPX
    ALXVP
    ALXVKQ
    ADCTFIXQQ
    ADCFFIXQQ
    ACNTTZDM
    ACNTLZDM
    ACFUGED
    ABRW
    ABRH
    ABRD
    AHASHSTP
    AHASHST
    AHASHCHKP
    AHASHCHK
    AXXSPLTIW
    AXXSPLTIDP
    AXXSPLTI32DX
    AXXPERMX
    AXXEVAL
    AXXBLENDVW
    AXXBLENDVH
    AXXBLENDVD
    AXXBLENDVB
    APSTXVP
    APSTXV
    APSTXSSP
    APSTXSD
    APSTW
    APSTQ
    APSTH
    APSTFS
    APSTFD
    APSTD
    APSTB
    APNOP
    APMXVI8GER4SPP
    APMXVI8GER4PP
    APMXVI8GER4
    APMXVI4GER8PP
    APMXVI4GER8
    APMXVI16GER2SPP
    APMXVI16GER2S
    APMXVI16GER2PP
    APMXVI16GER2
    APMXVF64GERPP
    APMXVF64GERPN
    APMXVF64GERNP
    APMXVF64GERNN
    APMXVF64GER
    APMXVF32GERPP
    APMXVF32GERPN
    APMXVF32GERNP
    APMXVF32GERNN
    APMXVF32GER
    APMXVF16GER2PP
    APMXVF16GER2PN
    APMXVF16GER2NP
    APMXVF16GER2NN
    APMXVF16GER2
    APMXVBF16GER2PP
    APMXVBF16GER2PN
    APMXVBF16GER2NP
    APMXVBF16GER2NN
    APMXVBF16GER2
    APLXVP
    APLXV
    APLXSSP
    APLXSD
    APLWZ
    APLWA
    APLQ
    APLHZ
    APLHA
    APLFS
    APLFD
    APLD
    APLBZ
    APADDI
    ALASTGEN
    AFIRSTGEN = AXXSETACCZ
)

* GENERAL: * * compiler allocates R3 up as temps * compiler allocates register variables R7-R27 * compiler allocates external registers R30 down * * compiler allocates register variables F17-F26 * compiler allocates external registers F26 down 

const (
    BIG = 32768 - 8
)
const (
    // The preferred hardware nop instruction.
    NOP = 0x60000000
)

Variables

var Anames = []string{
    obj.A_ARCHSPECIFIC: "ADD",
    "ADDCC",
    "ADDIS",
    "ADDV",
    "ADDVCC",
    "ADDC",
    "ADDCCC",
    "ADDCV",
    "ADDCVCC",
    "ADDME",
    "ADDMECC",
    "ADDMEVCC",
    "ADDMEV",
    "ADDE",
    "ADDECC",
    "ADDEVCC",
    "ADDEV",
    "ADDZE",
    "ADDZECC",
    "ADDZEVCC",
    "ADDZEV",
    "ADDEX",
    "AND",
    "ANDCC",
    "ANDN",
    "ANDNCC",
    "ANDISCC",
    "BC",
    "BCL",
    "BEQ",
    "BGE",
    "BGT",
    "BLE",
    "BLT",
    "BNE",
    "BVC",
    "BVS",
    "BDNZ",
    "BDZ",
    "CMP",
    "CMPU",
    "CMPEQB",
    "CNTLZW",
    "CNTLZWCC",
    "CRAND",
    "CRANDN",
    "CREQV",
    "CRNAND",
    "CRNOR",
    "CROR",
    "CRORN",
    "CRXOR",
    "DADD",
    "DADDQ",
    "DCMPO",
    "DCMPOQ",
    "DCMPU",
    "DCMPUQ",
    "DDIV",
    "DDIVQ",
    "DIVW",
    "DIVWCC",
    "DIVWVCC",
    "DIVWV",
    "DIVWU",
    "DIVWUCC",
    "DIVWUVCC",
    "DIVWUV",
    "DMUL",
    "DMULQ",
    "DSUB",
    "DSUBQ",
    "MODUD",
    "MODUW",
    "MODSD",
    "MODSW",
    "EQV",
    "EQVCC",
    "EXTSB",
    "EXTSBCC",
    "EXTSH",
    "EXTSHCC",
    "FABS",
    "FABSCC",
    "FADD",
    "FADDCC",
    "FADDS",
    "FADDSCC",
    "FCMPO",
    "FCMPU",
    "FCTIW",
    "FCTIWCC",
    "FCTIWZ",
    "FCTIWZCC",
    "FDIV",
    "FDIVCC",
    "FDIVS",
    "FDIVSCC",
    "FMADD",
    "FMADDCC",
    "FMADDS",
    "FMADDSCC",
    "FMOVD",
    "FMOVDCC",
    "FMOVDU",
    "FMOVS",
    "FMOVSU",
    "FMOVSX",
    "FMOVSZ",
    "FMSUB",
    "FMSUBCC",
    "FMSUBS",
    "FMSUBSCC",
    "FMUL",
    "FMULCC",
    "FMULS",
    "FMULSCC",
    "FNABS",
    "FNABSCC",
    "FNEG",
    "FNEGCC",
    "FNMADD",
    "FNMADDCC",
    "FNMADDS",
    "FNMADDSCC",
    "FNMSUB",
    "FNMSUBCC",
    "FNMSUBS",
    "FNMSUBSCC",
    "FRSP",
    "FRSPCC",
    "FSUB",
    "FSUBCC",
    "FSUBS",
    "FSUBSCC",
    "ISEL",
    "MOVMW",
    "LBAR",
    "LHAR",
    "LSW",
    "LWAR",
    "LWSYNC",
    "MOVDBR",
    "MOVWBR",
    "MOVB",
    "MOVBU",
    "MOVBZ",
    "MOVBZU",
    "MOVH",
    "MOVHBR",
    "MOVHU",
    "MOVHZ",
    "MOVHZU",
    "MOVW",
    "MOVWU",
    "MOVFL",
    "MOVCRFS",
    "MTFSB0",
    "MTFSB0CC",
    "MTFSB1",
    "MTFSB1CC",
    "MULHW",
    "MULHWCC",
    "MULHWU",
    "MULHWUCC",
    "MULLW",
    "MULLWCC",
    "MULLWVCC",
    "MULLWV",
    "NAND",
    "NANDCC",
    "NEG",
    "NEGCC",
    "NEGVCC",
    "NEGV",
    "NOR",
    "NORCC",
    "OR",
    "ORCC",
    "ORN",
    "ORNCC",
    "ORIS",
    "REM",
    "REMU",
    "RFI",
    "RLWMI",
    "RLWMICC",
    "RLWNM",
    "RLWNMCC",
    "CLRLSLWI",
    "SLW",
    "SLWCC",
    "SRW",
    "SRAW",
    "SRAWCC",
    "SRWCC",
    "STBCCC",
    "STHCCC",
    "STSW",
    "STWCCC",
    "SUB",
    "SUBCC",
    "SUBVCC",
    "SUBC",
    "SUBCCC",
    "SUBCV",
    "SUBCVCC",
    "SUBME",
    "SUBMECC",
    "SUBMEVCC",
    "SUBMEV",
    "SUBV",
    "SUBE",
    "SUBECC",
    "SUBEV",
    "SUBEVCC",
    "SUBZE",
    "SUBZECC",
    "SUBZEVCC",
    "SUBZEV",
    "SYNC",
    "XOR",
    "XORCC",
    "XORIS",
    "DCBF",
    "DCBI",
    "DCBST",
    "DCBT",
    "DCBTST",
    "DCBZ",
    "EIEIO",
    "ICBI",
    "ISYNC",
    "PTESYNC",
    "TLBIE",
    "TLBIEL",
    "TLBSYNC",
    "TW",
    "SYSCALL",
    "WORD",
    "RFCI",
    "FCPSGN",
    "FCPSGNCC",
    "FRES",
    "FRESCC",
    "FRIM",
    "FRIMCC",
    "FRIP",
    "FRIPCC",
    "FRIZ",
    "FRIZCC",
    "FRIN",
    "FRINCC",
    "FRSQRTE",
    "FRSQRTECC",
    "FSEL",
    "FSELCC",
    "FSQRT",
    "FSQRTCC",
    "FSQRTS",
    "FSQRTSCC",
    "CNTLZD",
    "CNTLZDCC",
    "CMPW",
    "CMPWU",
    "CMPB",
    "FTDIV",
    "FTSQRT",
    "DIVD",
    "DIVDCC",
    "DIVDE",
    "DIVDECC",
    "DIVDEU",
    "DIVDEUCC",
    "DIVDVCC",
    "DIVDV",
    "DIVDU",
    "DIVDUCC",
    "DIVDUVCC",
    "DIVDUV",
    "EXTSW",
    "EXTSWCC",
    "FCFID",
    "FCFIDCC",
    "FCFIDU",
    "FCFIDUCC",
    "FCFIDS",
    "FCFIDSCC",
    "FCTID",
    "FCTIDCC",
    "FCTIDZ",
    "FCTIDZCC",
    "LDAR",
    "MOVD",
    "MOVDU",
    "MOVWZ",
    "MOVWZU",
    "MULHD",
    "MULHDCC",
    "MULHDU",
    "MULHDUCC",
    "MULLD",
    "MULLDCC",
    "MULLDVCC",
    "MULLDV",
    "RFID",
    "RLDMI",
    "RLDMICC",
    "RLDIMI",
    "RLDIMICC",
    "RLDC",
    "RLDCCC",
    "RLDCR",
    "RLDCRCC",
    "RLDICR",
    "RLDICRCC",
    "RLDCL",
    "RLDCLCC",
    "RLDICL",
    "RLDICLCC",
    "RLDIC",
    "RLDICCC",
    "CLRLSLDI",
    "ROTL",
    "ROTLW",
    "SLBIA",
    "SLBIE",
    "SLBMFEE",
    "SLBMFEV",
    "SLBMTE",
    "SLD",
    "SLDCC",
    "SRD",
    "SRAD",
    "SRADCC",
    "SRDCC",
    "EXTSWSLI",
    "EXTSWSLICC",
    "STDCCC",
    "TD",
    "SETB",
    "DWORD",
    "REMD",
    "REMDU",
    "HRFID",
    "POPCNTD",
    "POPCNTW",
    "POPCNTB",
    "CNTTZW",
    "CNTTZWCC",
    "CNTTZD",
    "CNTTZDCC",
    "COPY",
    "PASTECC",
    "DARN",
    "MADDHD",
    "MADDHDU",
    "MADDLD",
    "LVEBX",
    "LVEHX",
    "LVEWX",
    "LVX",
    "LVXL",
    "LVSL",
    "LVSR",
    "STVEBX",
    "STVEHX",
    "STVEWX",
    "STVX",
    "STVXL",
    "VAND",
    "VANDC",
    "VNAND",
    "VOR",
    "VORC",
    "VNOR",
    "VXOR",
    "VEQV",
    "VADDUM",
    "VADDUBM",
    "VADDUHM",
    "VADDUWM",
    "VADDUDM",
    "VADDUQM",
    "VADDCU",
    "VADDCUQ",
    "VADDCUW",
    "VADDUS",
    "VADDUBS",
    "VADDUHS",
    "VADDUWS",
    "VADDSS",
    "VADDSBS",
    "VADDSHS",
    "VADDSWS",
    "VADDE",
    "VADDEUQM",
    "VADDECUQ",
    "VSUBUM",
    "VSUBUBM",
    "VSUBUHM",
    "VSUBUWM",
    "VSUBUDM",
    "VSUBUQM",
    "VSUBCU",
    "VSUBCUQ",
    "VSUBCUW",
    "VSUBUS",
    "VSUBUBS",
    "VSUBUHS",
    "VSUBUWS",
    "VSUBSS",
    "VSUBSBS",
    "VSUBSHS",
    "VSUBSWS",
    "VSUBE",
    "VSUBEUQM",
    "VSUBECUQ",
    "VMULESB",
    "VMULOSB",
    "VMULEUB",
    "VMULOUB",
    "VMULESH",
    "VMULOSH",
    "VMULEUH",
    "VMULOUH",
    "VMULESW",
    "VMULOSW",
    "VMULEUW",
    "VMULOUW",
    "VMULUWM",
    "VPMSUM",
    "VPMSUMB",
    "VPMSUMH",
    "VPMSUMW",
    "VPMSUMD",
    "VMSUMUDM",
    "VR",
    "VRLB",
    "VRLH",
    "VRLW",
    "VRLD",
    "VS",
    "VSLB",
    "VSLH",
    "VSLW",
    "VSL",
    "VSLO",
    "VSRB",
    "VSRH",
    "VSRW",
    "VSR",
    "VSRO",
    "VSLD",
    "VSRD",
    "VSA",
    "VSRAB",
    "VSRAH",
    "VSRAW",
    "VSRAD",
    "VSOI",
    "VSLDOI",
    "VCLZ",
    "VCLZB",
    "VCLZH",
    "VCLZW",
    "VCLZD",
    "VPOPCNT",
    "VPOPCNTB",
    "VPOPCNTH",
    "VPOPCNTW",
    "VPOPCNTD",
    "VCMPEQ",
    "VCMPEQUB",
    "VCMPEQUBCC",
    "VCMPEQUH",
    "VCMPEQUHCC",
    "VCMPEQUW",
    "VCMPEQUWCC",
    "VCMPEQUD",
    "VCMPEQUDCC",
    "VCMPGT",
    "VCMPGTUB",
    "VCMPGTUBCC",
    "VCMPGTUH",
    "VCMPGTUHCC",
    "VCMPGTUW",
    "VCMPGTUWCC",
    "VCMPGTUD",
    "VCMPGTUDCC",
    "VCMPGTSB",
    "VCMPGTSBCC",
    "VCMPGTSH",
    "VCMPGTSHCC",
    "VCMPGTSW",
    "VCMPGTSWCC",
    "VCMPGTSD",
    "VCMPGTSDCC",
    "VCMPNEZB",
    "VCMPNEZBCC",
    "VCMPNEB",
    "VCMPNEBCC",
    "VCMPNEH",
    "VCMPNEHCC",
    "VCMPNEW",
    "VCMPNEWCC",
    "VPERM",
    "VPERMXOR",
    "VPERMR",
    "VBPERMQ",
    "VBPERMD",
    "VSEL",
    "VSPLTB",
    "VSPLTH",
    "VSPLTW",
    "VSPLTISB",
    "VSPLTISH",
    "VSPLTISW",
    "VCIPH",
    "VCIPHER",
    "VCIPHERLAST",
    "VNCIPH",
    "VNCIPHER",
    "VNCIPHERLAST",
    "VSBOX",
    "VSHASIGMA",
    "VSHASIGMAW",
    "VSHASIGMAD",
    "VMRGEW",
    "VMRGOW",
    "VCLZLSBB",
    "VCTZLSBB",
    "LXV",
    "LXVL",
    "LXVLL",
    "LXVD2X",
    "LXVW4X",
    "LXVH8X",
    "LXVB16X",
    "LXVX",
    "LXVDSX",
    "STXV",
    "STXVL",
    "STXVLL",
    "STXVD2X",
    "STXVW4X",
    "STXVH8X",
    "STXVB16X",
    "STXVX",
    "LXSDX",
    "STXSDX",
    "LXSIWAX",
    "LXSIWZX",
    "STXSIWX",
    "MFVSRD",
    "MFFPRD",
    "MFVRD",
    "MFVSRWZ",
    "MFVSRLD",
    "MTVSRD",
    "MTFPRD",
    "MTVRD",
    "MTVSRWA",
    "MTVSRWZ",
    "MTVSRDD",
    "MTVSRWS",
    "XXLAND",
    "XXLANDC",
    "XXLEQV",
    "XXLNAND",
    "XXLOR",
    "XXLORC",
    "XXLNOR",
    "XXLORQ",
    "XXLXOR",
    "XXSEL",
    "XXMRGHW",
    "XXMRGLW",
    "XXSPLTW",
    "XXSPLTIB",
    "XXPERM",
    "XXPERMDI",
    "XXSLDWI",
    "XXBRQ",
    "XXBRD",
    "XXBRW",
    "XXBRH",
    "XSCVDPSP",
    "XSCVSPDP",
    "XSCVDPSPN",
    "XSCVSPDPN",
    "XVCVDPSP",
    "XVCVSPDP",
    "XSCVDPSXDS",
    "XSCVDPSXWS",
    "XSCVDPUXDS",
    "XSCVDPUXWS",
    "XSCVSXDDP",
    "XSCVUXDDP",
    "XSCVSXDSP",
    "XSCVUXDSP",
    "XVCVDPSXDS",
    "XVCVDPSXWS",
    "XVCVDPUXDS",
    "XVCVDPUXWS",
    "XVCVSPSXDS",
    "XVCVSPSXWS",
    "XVCVSPUXDS",
    "XVCVSPUXWS",
    "XVCVSXDDP",
    "XVCVSXWDP",
    "XVCVUXDDP",
    "XVCVUXWDP",
    "XVCVSXDSP",
    "XVCVSXWSP",
    "XVCVUXDSP",
    "XVCVUXWSP",
    "XSMAXJDP",
    "XSMINJDP",
    "LASTAOUT",
}
var GenAnames = []string{
    "XXSETACCZ",
    "XXMTACC",
    "XXMFACC",
    "XXGENPCVWM",
    "XXGENPCVHM",
    "XXGENPCVDM",
    "XXGENPCVBM",
    "XVTLSBB",
    "XVI8GER4SPP",
    "XVI8GER4PP",
    "XVI8GER4",
    "XVI4GER8PP",
    "XVI4GER8",
    "XVI16GER2SPP",
    "XVI16GER2S",
    "XVI16GER2PP",
    "XVI16GER2",
    "XVF64GERPP",
    "XVF64GERPN",
    "XVF64GERNP",
    "XVF64GERNN",
    "XVF64GER",
    "XVF32GERPP",
    "XVF32GERPN",
    "XVF32GERNP",
    "XVF32GERNN",
    "XVF32GER",
    "XVF16GER2PP",
    "XVF16GER2PN",
    "XVF16GER2NP",
    "XVF16GER2NN",
    "XVF16GER2",
    "XVCVSPBF16",
    "XVCVBF16SPN",
    "XVBF16GER2PP",
    "XVBF16GER2PN",
    "XVBF16GER2NP",
    "XVBF16GER2NN",
    "XVBF16GER2",
    "XSMINCQP",
    "XSMAXCQP",
    "XSCVUQQP",
    "XSCVSQQP",
    "XSCVQPUQZ",
    "XSCVQPSQZ",
    "XSCMPGTQP",
    "XSCMPGEQP",
    "XSCMPEQQP",
    "VSTRIHRCC",
    "VSTRIHR",
    "VSTRIHLCC",
    "VSTRIHL",
    "VSTRIBRCC",
    "VSTRIBR",
    "VSTRIBLCC",
    "VSTRIBL",
    "VSRQ",
    "VSRDBI",
    "VSRAQ",
    "VSLQ",
    "VSLDBI",
    "VRLQNM",
    "VRLQMI",
    "VRLQ",
    "VPEXTD",
    "VPDEPD",
    "VMULOUD",
    "VMULOSD",
    "VMULLD",
    "VMULHUW",
    "VMULHUD",
    "VMULHSW",
    "VMULHSD",
    "VMULEUD",
    "VMULESD",
    "VMSUMCUD",
    "VMODUW",
    "VMODUQ",
    "VMODUD",
    "VMODSW",
    "VMODSQ",
    "VMODSD",
    "VINSWVRX",
    "VINSWVLX",
    "VINSWRX",
    "VINSWLX",
    "VINSW",
    "VINSHVRX",
    "VINSHVLX",
    "VINSHRX",
    "VINSHLX",
    "VINSDRX",
    "VINSDLX",
    "VINSD",
    "VINSBVRX",
    "VINSBVLX",
    "VINSBRX",
    "VINSBLX",
    "VGNB",
    "VEXTSD2Q",
    "VEXTRACTWM",
    "VEXTRACTQM",
    "VEXTRACTHM",
    "VEXTRACTDM",
    "VEXTRACTBM",
    "VEXTDUWVRX",
    "VEXTDUWVLX",
    "VEXTDUHVRX",
    "VEXTDUHVLX",
    "VEXTDUBVRX",
    "VEXTDUBVLX",
    "VEXTDDVRX",
    "VEXTDDVLX",
    "VEXPANDWM",
    "VEXPANDQM",
    "VEXPANDHM",
    "VEXPANDDM",
    "VEXPANDBM",
    "VDIVUW",
    "VDIVUQ",
    "VDIVUD",
    "VDIVSW",
    "VDIVSQ",
    "VDIVSD",
    "VDIVEUW",
    "VDIVEUQ",
    "VDIVEUD",
    "VDIVESW",
    "VDIVESQ",
    "VDIVESD",
    "VCTZDM",
    "VCNTMBW",
    "VCNTMBH",
    "VCNTMBD",
    "VCNTMBB",
    "VCMPUQ",
    "VCMPSQ",
    "VCMPGTUQCC",
    "VCMPGTUQ",
    "VCMPGTSQCC",
    "VCMPGTSQ",
    "VCMPEQUQCC",
    "VCMPEQUQ",
    "VCLZDM",
    "VCLRRB",
    "VCLRLB",
    "VCFUGED",
    "STXVRWX",
    "STXVRHX",
    "STXVRDX",
    "STXVRBX",
    "STXVPX",
    "STXVP",
    "SETNBCR",
    "SETNBC",
    "SETBCR",
    "SETBC",
    "PEXTD",
    "PDEPD",
    "MTVSRWM",
    "MTVSRQM",
    "MTVSRHM",
    "MTVSRDM",
    "MTVSRBMI",
    "MTVSRBM",
    "LXVRWX",
    "LXVRHX",
    "LXVRDX",
    "LXVRBX",
    "LXVPX",
    "LXVP",
    "LXVKQ",
    "DCTFIXQQ",
    "DCFFIXQQ",
    "CNTTZDM",
    "CNTLZDM",
    "CFUGED",
    "BRW",
    "BRH",
    "BRD",
    "HASHSTP",
    "HASHST",
    "HASHCHKP",
    "HASHCHK",
    "XXSPLTIW",
    "XXSPLTIDP",
    "XXSPLTI32DX",
    "XXPERMX",
    "XXEVAL",
    "XXBLENDVW",
    "XXBLENDVH",
    "XXBLENDVD",
    "XXBLENDVB",
    "PSTXVP",
    "PSTXV",
    "PSTXSSP",
    "PSTXSD",
    "PSTW",
    "PSTQ",
    "PSTH",
    "PSTFS",
    "PSTFD",
    "PSTD",
    "PSTB",
    "PNOP",
    "PMXVI8GER4SPP",
    "PMXVI8GER4PP",
    "PMXVI8GER4",
    "PMXVI4GER8PP",
    "PMXVI4GER8",
    "PMXVI16GER2SPP",
    "PMXVI16GER2S",
    "PMXVI16GER2PP",
    "PMXVI16GER2",
    "PMXVF64GERPP",
    "PMXVF64GERPN",
    "PMXVF64GERNP",
    "PMXVF64GERNN",
    "PMXVF64GER",
    "PMXVF32GERPP",
    "PMXVF32GERPN",
    "PMXVF32GERNP",
    "PMXVF32GERNN",
    "PMXVF32GER",
    "PMXVF16GER2PP",
    "PMXVF16GER2PN",
    "PMXVF16GER2NP",
    "PMXVF16GER2NN",
    "PMXVF16GER2",
    "PMXVBF16GER2PP",
    "PMXVBF16GER2PN",
    "PMXVBF16GER2NP",
    "PMXVBF16GER2NN",
    "PMXVBF16GER2",
    "PLXVP",
    "PLXV",
    "PLXSSP",
    "PLXSD",
    "PLWZ",
    "PLWA",
    "PLQ",
    "PLHZ",
    "PLHA",
    "PLFS",
    "PLFD",
    "PLD",
    "PLBZ",
    "PADDI",
}
var GenOpcodes = [...]uint32{
    0x7c030162,
    0x7c010162,
    0x7c000162,
    0xf0000768,
    0xf000072a,
    0xf000076a,
    0xf0000728,
    0xf002076c,
    0xec000318,
    0xec000010,
    0xec000018,
    0xec000110,
    0xec000118,
    0xec000150,
    0xec000158,
    0xec000358,
    0xec000258,
    0xec0001d0,
    0xec0005d0,
    0xec0003d0,
    0xec0007d0,
    0xec0001d8,
    0xec0000d0,
    0xec0004d0,
    0xec0002d0,
    0xec0006d0,
    0xec0000d8,
    0xec000090,
    0xec000490,
    0xec000290,
    0xec000690,
    0xec000098,
    0xf011076c,
    0xf010076c,
    0xec000190,
    0xec000590,
    0xec000390,
    0xec000790,
    0xec000198,
    0xfc0005c8,
    0xfc000548,
    0xfc030688,
    0xfc0b0688,
    0xfc000688,
    0xfc080688,
    0xfc0001c8,
    0xfc000188,
    0xfc000088,
    0x1003040d,
    0x1003000d,
    0x1002040d,
    0x1002000d,
    0x1001040d,
    0x1001000d,
    0x1000040d,
    0x1000000d,
    0x10000205,
    0x10000216,
    0x10000305,
    0x10000105,
    0x10000016,
    0x10000145,
    0x10000045,
    0x10000005,
    0x1000058d,
    0x100005cd,
    0x100000c8,
    0x100001c8,
    0x100001c9,
    0x10000289,
    0x100002c9,
    0x10000389,
    0x100003c9,
    0x100002c8,
    0x100003c8,
    0x10000017,
    0x1000068b,
    0x1000060b,
    0x100006cb,
    0x1000078b,
    0x1000070b,
    0x100007cb,
    0x1000018f,
    0x1000008f,
    0x1000038f,
    0x1000028f,
    0x100000cf,
    0x1000014f,
    0x1000004f,
    0x1000034f,
    0x1000024f,
    0x100003cf,
    0x100002cf,
    0x100001cf,
    0x1000010f,
    0x1000000f,
    0x1000030f,
    0x1000020f,
    0x100004cc,
    0x101b0602,
    0x100a0642,
    0x100c0642,
    0x10090642,
    0x100b0642,
    0x10080642,
    0x1000001d,
    0x1000001c,
    0x1000001b,
    0x1000001a,
    0x10000019,
    0x10000018,
    0x1000001f,
    0x1000001e,
    0x10020642,
    0x10040642,
    0x10010642,
    0x10030642,
    0x10000642,
    0x1000008b,
    0x1000000b,
    0x100000cb,
    0x1000018b,
    0x1000010b,
    0x100001cb,
    0x1000028b,
    0x1000020b,
    0x100002cb,
    0x1000038b,
    0x1000030b,
    0x100003cb,
    0x100007c4,
    0x101c0642,
    0x101a0642,
    0x101e0642,
    0x10180642,
    0x10000101,
    0x10000141,
    0x10000687,
    0x10000287,
    0x10000787,
    0x10000387,
    0x100005c7,
    0x100001c7,
    0x10000784,
    0x100001cd,
    0x1000018d,
    0x1000054d,
    0x7c00019a,
    0x7c00015a,
    0x7c0001da,
    0x7c00011a,
    0x7c00039a,
    0x18000001,
    0x7c0003c0,
    0x7c000380,
    0x7c000340,
    0x7c000300,
    0x7c000178,
    0x7c000138,
    0x10120642,
    0x10140642,
    0x10110642,
    0x10130642,
    0x10000014,
    0x10100642,
    0x7c00009a,
    0x7c00005a,
    0x7c0000da,
    0x7c00001a,
    0x7c00029a,
    0x18000000,
    0xf01f02d0,
    0xfc0107c4,
    0xfc0007c4,
    0x7c000476,
    0x7c000076,
    0x7c0001b8,
    0x7c000136,
    0x7c0001b6,
    0x7c000176,
    0x7c000524,
    0x7c0005a4,
    0x7c000564,
    0x7c0005e4,
    0x80060000,
    0x80040000,
    0x80000000,
    0x88000000,
    0x88000010,
    0x84000020,
    0x84000010,
    0x84000030,
    0x84000000,
    0xf8000000,
    0xd8000000,
    0xbc000000,
    0xb8000000,
    0x90000000,
    0xf0000000,
    0xb0000000,
    0xd0000000,
    0xd8000000,
    0xf4000000,
    0x98000000,
    0x00000000,
    0xec000318,
    0xec000010,
    0xec000018,
    0xec000110,
    0xec000118,
    0xec000150,
    0xec000158,
    0xec000358,
    0xec000258,
    0xec0001d0,
    0xec0005d0,
    0xec0003d0,
    0xec0007d0,
    0xec0001d8,
    0xec0000d0,
    0xec0004d0,
    0xec0002d0,
    0xec0006d0,
    0xec0000d8,
    0xec000090,
    0xec000490,
    0xec000290,
    0xec000690,
    0xec000098,
    0xec000190,
    0xec000590,
    0xec000390,
    0xec000790,
    0xec000198,
    0xe8000000,
    0xc8000000,
    0xac000000,
    0xa8000000,
    0x80000000,
    0xa4000000,
    0xe0000000,
    0xa0000000,
    0xa8000000,
    0xc0000000,
    0xc8000000,
    0xe4000000,
    0x88000000,
    0x38000000,
}
var GenPfxOpcodes = [...]uint32{
    0x05000000,
    0x05000000,
    0x05000000,
    0x05000000,
    0x05000000,
    0x05000000,
    0x05000000,
    0x05000000,
    0x05000000,
    0x04000000,
    0x04000000,
    0x04000000,
    0x04000000,
    0x06000000,
    0x04000000,
    0x06000000,
    0x06000000,
    0x06000000,
    0x04000000,
    0x06000000,
    0x07000000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x07900000,
    0x04000000,
    0x04000000,
    0x04000000,
    0x04000000,
    0x06000000,
    0x04000000,
    0x04000000,
    0x06000000,
    0x06000000,
    0x06000000,
    0x06000000,
    0x04000000,
    0x06000000,
    0x06000000,
}
var Linkppc64 = obj.LinkArch{
    Arch:           sys.ArchPPC64,
    Init:           buildop,
    Preprocess:     preprocess,
    Assemble:       span9,
    Progedit:       progedit,
    UnaryDst:       unaryDst,
    DWARFRegisters: PPC64DWARFRegisters,
}
var Linkppc64le = obj.LinkArch{
    Arch:           sys.ArchPPC64LE,
    Init:           buildop,
    Preprocess:     preprocess,
    Assemble:       span9,
    Progedit:       progedit,
    UnaryDst:       unaryDst,
    DWARFRegisters: PPC64DWARFRegisters,
}

OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture 

var PPC64DWARFRegisters = map[int16]int16{}

func AOP_DQ 

func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32

DQ-form, VSR register, register + offset operands

func AOP_EXTSWSLI 

func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32

func AOP_IIRR 

func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32

VX-form 2-register + ST + SIX operands

func AOP_IR 

func AOP_IR(op uint32, d uint32, simm uint32) uint32

VX-form 1-register + SIM operands

func AOP_IRR 

func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32

func AOP_IRRR 

func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32

VA-form 3-register + SHB operands

func AOP_ISEL 

func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32

func AOP_MD 

func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32

MD-form 2-register, 2 6-bit immediate operands

func AOP_MDS 

func AOP_MDS(op, to, from, rsh, m uint32) uint32

MDS-form 3-register, 1 6-bit immediate operands. rsh argument is a register.

func AOP_PFX_00_8LS 

func AOP_PFX_00_8LS(r, ie uint32) uint32

func AOP_PFX_10_MLS 

func AOP_PFX_10_MLS(r, ie uint32) uint32

func AOP_RR 

func AOP_RR(op uint32, d uint32, a uint32) uint32

VX-form 2-register operands, r/none/r

func AOP_RRR 

func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32

the order is dest, a/s, b/imm for both arithmetic and logical operations.

func AOP_RRRI 

func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32

X-form, 3-register operands + EH field

func AOP_RRRR 

func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32

VA-form 4-register operands

func AOP_VIRR 

func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32

VX-form 2-register + UIM operands

func AOP_XX1 

func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32

XX1-form 3-register operands, 1 VSR operand

func AOP_XX2 

func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32

XX2-form 3-register operands, 2 VSR operands

func AOP_XX3 

func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32

XX3-form 3 VSR operands

func AOP_XX3I 

func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32

XX3-form 3 VSR operands + immediate

func AOP_XX4 

func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32

XX4-form, 4 VSR operands

func AOP_Z23I 

func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32

Z23-form, 3-register operands + CY field

func ConstantToCRbit 

func ConstantToCRbit(c int64) (int16, bool)

func DRconv 

func DRconv(a int) string

func LOP_IRR 

func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32

func LOP_RRR 

func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32

func NeedTOCpointer 

func NeedTOCpointer(ctxt *obj.Link) bool

Determine if the build configuration requires a TOC pointer. It is assumed this always called after buildop.

func OPCC 

func OPCC(o uint32, xo uint32, rc uint32) uint32

func OPDQ 

func OPDQ(o uint32, xo uint32, oe uint32) uint32

func OPMD 

func OPMD(o, xo, rc uint32) uint32

Generate MD-form opcode

func OPVC 

func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32

func OPVCC 

func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32

func OPVX 

func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32

func OPVXX1 

func OPVXX1(o uint32, xo uint32, oe uint32) uint32

func OPVXX2 

func OPVXX2(o uint32, xo uint32, oe uint32) uint32

func OPVXX2VA 

func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32

func OPVXX3 

func OPVXX3(o uint32, xo uint32, oe uint32) uint32

func OPVXX4 

func OPVXX4(o uint32, xo uint32, oe uint32) uint32

func OP_BC 

func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32

func OP_BCR 

func OP_BCR(op uint32, bo uint32, bi uint32) uint32

func OP_BR 

func OP_BR(op uint32, li uint32, aa uint32) uint32

func OP_RLW 

func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32

type Optab 

type Optab struct {
    // contains filtered or unexported fields
}

type PrefixableOptab

These are opcodes above which may generate different sequences depending on whether prefix opcode support is available 

type PrefixableOptab struct {
    Optab
    // contains filtered or unexported fields
}
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